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* Fixing old emails and names in copyrightsgatecat2021-06-127-9/+9
* interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
* interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
* interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
* interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
* interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
* fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
* Remove redundant code after hashlib movegatecat2021-06-021-65/+0
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
* Using hashlib in archesgatecat2021-06-0225-326/+176
* Use hashlib for core netlist structuresgatecat2021-06-025-12/+14
* Add hash() member functionsgatecat2021-06-021-0/+5
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-0110-1/+82
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
* Run clangformatgatecat2021-05-162-5/+7
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
* interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
* interchange: Initial global routing implementationgatecat2021-05-073-0/+222
* interchange: Add more global cell infogatecat2021-05-071-1/+14
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+15
* interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
* interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
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| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
* | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
* | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
* | Add Python bindings for placement testsgatecat2021-04-151-0/+5
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1420-70/+135
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| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
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* / Hash table refactoringgatecat2021-04-146-10/+11
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* interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
* clangformatgatecat2021-04-128-133/+134
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 00:33:59 +0000