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* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
|\ | | | | interchange: Fix handling of constants in macros
| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #743 from YosysHQ/gatecat/site-rsv-portsgatecat2021-07-015-0/+69
|\ \ | | | | | | interchange: Reserve site ports only reachable from dedicated routing
| * | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-015-0/+69
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* / interchange: phys: do not output nets which have no usersAlessandro Comodi2021-07-011-1/+12
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Place IO macro content based on routinggatecat2021-06-301-0/+79
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Track the macros that cells have been expanded fromgatecat2021-06-293-0/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #736 from YosysHQ/gatecat/pp-multi-outputgatecat2021-06-281-13/+2
|\ | | | | interchange: Allow site wires driven by more than one bel
| * interchange: Allow site wires driven by more than one belgatecat2021-06-281-13/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Handle disconnected bel pins in dedicated interconnectgatecat2021-06-281-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #728 from YosysHQ/gatecat/nexus-ramgatecat2021-06-156-0/+382
|\ | | | | interchange/nexus: Add RAM techmap rule and a RAM test
| * nexus: Add modified version of RAM testgatecat2021-06-155-0/+206
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Add PDPSC16K->PDPSC16K_MODE to remap rulesgatecat2021-06-151-0/+176
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Cope with undriven nets in more placesgatecat2021-06-143-5/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-127-9/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
| | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
* Remove redundant code after hashlib movegatecat2021-06-021-65/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-0225-326/+176
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-025-12/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-0110-1/+82
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
| | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Run clangformatgatecat2021-05-162-5/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
| | | | | | | | | | | | During general routing, the only site pips that can be allowed are those which connect a site wire to the routing interface. This might be too restrictive when dealing with architectures that require more than one site PIPs to route from a driver within a site to the routing interface (which is something that should be allowed in the interchange). Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Initial global routing implementationgatecat2021-05-073-0/+222
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add more global cell infogatecat2021-05-071-1/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+15
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 13:16:44 +0000