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* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
| | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #661 from litghost/document_site_routergatecat2021-04-061-10/+58
|\ | | | | [interchange] Add some documentation for the site router.
| * [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #657 from acomodi/interchange-counter-multi-boardgatecat2021-04-065-23/+25
|\ \ | |/ |/| interchange: counter: testing on multiple boards
| * interchange: counter: testing on multiple boardsAlessandro Comodi2021-04-015-23/+25
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-013-2/+12
|/ | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #646 from YosysHQ/gatecat/nexus-cmakegatecat2021-03-3113-126/+368
|\ | | | | fpga_interchange: Add CMake support for Nexus/prjoxide
| * interchange: Fix nexus cmake review commentsgatecat2021-03-313-9/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Split xc7 and nexus chipdb cmakegatecat2021-03-303-243/+245
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add Nexus LUT testgatecat2021-03-307-19/+139
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add Nexus to CIgatecat2021-03-303-1/+11
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add CMake support for Nexus/prjoxidegatecat2021-03-303-0/+115
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Fix bug where DedicateInterconnect incorrectly allows some placement.Keith Rothman2021-03-302-10/+23
| | | | | | | | | | | | | | This occurs when the driver pin and sink pin are part of the same site, but not reachable with site routing only. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
|/ | | | | | Previous code allowed router to entire sites with no sinks. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Fix illegal placementsgatecat2021-03-301-6/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #645 from litghost/add_counter_and_ramgatecat2021-03-2922-335/+1218
|\ | | | | FPGA interchange: Add counter and ram tests
| * Update README with latest develpment progress.Keith Rothman2021-03-252-146/+39
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
| | | | | | | | | | | | | | This resulted in valid site routing solutions being missed. Underlying bug was an off-by-one error when unwinding a failed solution. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Implement debugging tools for site router.Keith Rothman2021-03-257-23/+166
| | | | | | | | | | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add targets to generate YAML outputs for DeviceResource files.Keith Rothman2021-03-251-0/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-255-104/+174
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fixup some of the re-mapping logic.Keith Rothman2021-03-252-27/+75
| | | | | | | | | | | | | | - Add IDEMPOTENT_CHECK define to perform some expected idempotent operations more than once to verify they work as expected. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-257-58/+457
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-252-9/+14
| | | | | | | | | | | | | | If get_net_type was called before the driver was placed, it could return the wrong value. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Enable counter tests and add RAM tests.Keith Rothman2021-03-256-2/+284
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | interchange: add archcheck tests to all-device-test targetAlessandro Comodi2021-03-261-1/+6
|/ | | | | | | This increases parallelism and should make the FPGA interchange CI faster Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* gh-actions: interchange: multiple jobs, one for each deviceAlessandro Comodi2021-03-242-1/+5
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: examples: remove unused makefilesAlessandro Comodi2021-03-242-99/+0
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: devices: bel_bucket_seeds -> device_configAlessandro Comodi2021-03-233-3/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: added boards and group testing across multiple boardsAlessandro Comodi2021-03-2310-45/+155
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: add test data for new architecturesAlessandro Comodi2021-03-233-0/+108
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: use higher java heap spaceAlessandro Comodi2021-03-233-3/+4
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: add more devicesAlessandro Comodi2021-03-238-3/+91
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-234-10/+29
|\ | | | | [FPGA interchange] Add support for global buffers from chipdb.
| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-234-10/+29
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-232-4/+27
|\ \ | | | | | | [FPGA interchange] Convert some string constants to IdString.
| * | [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-232-4/+27
| | | | | | | | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #640 from litghost/inversion_logicgatecat2021-03-237-8/+131
|\ \ \ | | |/ | |/| Initial inverter logic for FPGA interchange
| * | Initial version of inverter logic.Keith Rothman2021-03-237-8/+131
| | | | | | | | | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #639 from litghost/parameter_iterationgatecat2021-03-235-42/+315
|\| | | |/ |/| Update parameter processing based on new DeviceResources metadata
| * Update FPGA interchange chipdb to v4 with inverter data.Keith Rothman2021-03-231-1/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-234-41/+284
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Update latest version of FPGA interchange schema.Keith Rothman2021-03-231-1/+10
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #642 from YosysHQ/gatecat/missing-cell-pingatecat2021-03-231-0/+3
|\ \ | |/ |/| interchange: Add nice error for missing cell pins
| * interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Initial lookahead for FPGA interchange.Keith Rothman2021-03-2313-13/+2682
|/ | | | | | | | | Currently the lookahead is disabled by default because of the time to compute and RAM usage. However it does appear to work reasonably well in testing. Further effort is required to lower RAM usage after initial computation, and explore trade-off for cheaper time to compute. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #638 from litghost/fixup_physical_netlist_writergatecat2021-03-221-11/+93
|\ | | | | Correct some bugs in writing of physical netlist w.r.t. site sources.
| * Correct some bugs in writing of physical netlist w.r.t. site sources.Keith Rothman2021-03-221-11/+93
| | | | | | | | | | | | | | Local site sources should have their driving BEL pin included in the net so that the site wire is driven by an output BEL pin. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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