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fpga_interchange
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Author
Age
Files
Lines
*
Added computing and reporting LUT mapping cache size
Maciej Kurc
2021-07-16
2
-0
/
+37
*
Fixed assertion typos
Maciej Kurc
2021-07-16
1
-2
/
+2
*
Migrated C arrays to std::array containers.
Maciej Kurc
2021-07-16
2
-9
/
+31
*
LUT mapping ceche optimizations 2
Maciej Kurc
2021-07-16
3
-93
/
+17
*
LUT mapping cache optimizations 1
Maciej Kurc
2021-07-16
2
-32
/
+48
*
Working site LUT mapping cache
Maciej Kurc
2021-07-16
7
-42
/
+470
*
interchange: Allow pseudo pip wires to overlap with bound site wires on the s...
gatecat
2021-07-06
2
-9
/
+5
*
interchange: Improve search for PAD-attached bels
gatecat
2021-07-06
2
-41
/
+32
*
interchange: tests: add obuftds test
Alessandro Comodi
2021-07-06
6
-0
/
+80
*
interchange: phys: skip only nets writing on disconnected out ports
Alessandro Comodi
2021-07-02
1
-2
/
+13
*
Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const
gatecat
2021-07-01
1
-5
/
+9
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\
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*
interchange: Handle canInvert PIPs when processing preferred constants
gatecat
2021-07-01
1
-5
/
+9
*
|
interchange: Handle case where routing source is a node
gatecat
2021-07-01
1
-0
/
+5
|
/
*
Merge pull request #744 from YosysHQ/gatecat/const-in-macro
gatecat
2021-07-01
1
-1
/
+1
|
\
|
*
interchange: Fix handling of constants in macros
gatecat
2021-07-01
1
-1
/
+1
*
|
Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports
gatecat
2021-07-01
5
-0
/
+69
|
\
\
|
*
|
interchange: Reserve site ports only reachable from dedicated routing
gatecat
2021-07-01
5
-0
/
+69
|
|
/
*
/
interchange: phys: do not output nets which have no users
Alessandro Comodi
2021-07-01
1
-1
/
+12
|
/
*
interchange: fix dedicated interconnect exploration
Alessandro Comodi
2021-06-30
1
-8
/
+14
*
interchange: Fix dedicated interconnect check when site is the same
gatecat
2021-06-30
1
-1
/
+4
*
interchange: Place IO macro content based on routing
gatecat
2021-06-30
1
-0
/
+79
*
interchange: Track the macros that cells have been expanded from
gatecat
2021-06-29
3
-0
/
+8
*
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output
gatecat
2021-06-28
1
-13
/
+2
|
\
|
*
interchange: Allow site wires driven by more than one bel
gatecat
2021-06-28
1
-13
/
+2
*
|
interchange: Handle disconnected bel pins in dedicated interconnect
gatecat
2021-06-28
1
-1
/
+1
|
/
*
interchange: arch: move macro expansion step before ios packing
Alessandro Comodi
2021-06-18
1
-1
/
+1
*
Merge pull request #728 from YosysHQ/gatecat/nexus-ram
gatecat
2021-06-15
6
-0
/
+382
|
\
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*
nexus: Add modified version of RAM test
gatecat
2021-06-15
5
-0
/
+206
|
*
nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules
gatecat
2021-06-15
1
-0
/
+176
*
|
interchange: fix phys net writer
Alessandro Comodi
2021-06-15
1
-5
/
+2
|
/
*
interchange: Cope with undriven nets in more places
gatecat
2021-06-14
3
-5
/
+9
*
Fixing old emails and names in copyrights
gatecat
2021-06-12
7
-9
/
+9
*
interchange: clusters: always get cell bel map and add asserts
Alessandro Comodi
2021-06-11
1
-23
/
+13
*
interchange: run clang formatter
Alessandro Comodi
2021-06-11
2
-22
/
+18
*
interchange: clusters: adjust comments
Alessandro Comodi
2021-06-11
2
-11
/
+16
*
interchange: increase chipinfo version
Alessandro Comodi
2021-06-11
1
-1
/
+1
*
interchange: tests: counter: emit carries for xc7
Alessandro Comodi
2021-06-11
2
-4
/
+6
*
interchange: add support for generating BEL clusters
Alessandro Comodi
2021-06-11
9
-24
/
+713
*
fpga_interchange: Add site router tests
Tomasz Michalak
2021-06-11
1
-0
/
+3
*
Remove redundant code after hashlib move
gatecat
2021-06-02
1
-65
/
+0
*
Use hashlib in most remaining code
gatecat
2021-06-02
1
-2
/
+2
*
Using hashlib in arches
gatecat
2021-06-02
25
-326
/
+176
*
Use hashlib for core netlist structures
gatecat
2021-06-02
5
-12
/
+14
*
Add hash() member functions
gatecat
2021-06-02
1
-0
/
+5
*
interchange: Add LIFCL-40 EVN tests
gatecat
2021-06-01
10
-1
/
+82
*
interchange: Add macro parameter mapping
gatecat
2021-05-21
2
-3
/
+53
*
interchange: Don't error out on missing cell ports
gatecat
2021-05-21
2
-2
/
+3
*
interchange: Add LUTRAM test
gatecat
2021-05-21
6
-0
/
+169
*
interchange: Preliminary implementation of macro expansion
gatecat
2021-05-21
3
-0
/
+116
*
interchange: Add macro param map rules to chipdb
gatecat
2021-05-21
1
-0
/
+24
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