aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange
Commit message (Expand)AuthorAgeFilesLines
...
| * interchange: Fix nexus cmake review commentsgatecat2021-03-313-9/+4
| * interchange: Split xc7 and nexus chipdb cmakegatecat2021-03-303-243/+245
| * interchange: Add Nexus LUT testgatecat2021-03-307-19/+139
| * interchange: Add Nexus to CIgatecat2021-03-303-1/+11
| * interchange: Add CMake support for Nexus/prjoxidegatecat2021-03-303-0/+115
* | Fix bug where DedicateInterconnect incorrectly allows some placement.Keith Rothman2021-03-302-10/+23
* | [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
|/
* interchange: Fix illegal placementsgatecat2021-03-301-6/+5
* Merge pull request #645 from litghost/add_counter_and_ramgatecat2021-03-2922-335/+1218
|\
| * Update README with latest develpment progress.Keith Rothman2021-03-252-146/+39
| * interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
| * Implement debugging tools for site router.Keith Rothman2021-03-257-23/+166
| * Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
| * Add targets to generate YAML outputs for DeviceResource files.Keith Rothman2021-03-251-0/+22
| * Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-255-104/+174
| * Fixup some of the re-mapping logic.Keith Rothman2021-03-252-27/+75
| * Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-257-58/+457
| * [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-252-9/+14
| * Enable counter tests and add RAM tests.Keith Rothman2021-03-256-2/+284
* | interchange: add archcheck tests to all-device-test targetAlessandro Comodi2021-03-261-1/+6
|/
* gh-actions: interchange: multiple jobs, one for each deviceAlessandro Comodi2021-03-242-1/+5
* interchange: examples: remove unused makefilesAlessandro Comodi2021-03-242-99/+0
* interchange: devices: bel_bucket_seeds -> device_configAlessandro Comodi2021-03-233-3/+3
* interchange: added boards and group testing across multiple boardsAlessandro Comodi2021-03-2310-45/+155
* fpga_interchange: add test data for new architecturesAlessandro Comodi2021-03-233-0/+108
* fpga_interchange: use higher java heap spaceAlessandro Comodi2021-03-233-3/+4
* fpga_interchange: add more devicesAlessandro Comodi2021-03-238-3/+91
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-234-10/+29
|\
| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-234-10/+29
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-232-4/+27
|\ \
| * | [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-232-4/+27
* | | Merge pull request #640 from litghost/inversion_logicgatecat2021-03-237-8/+131
|\ \ \ | | |/ | |/|
| * | Initial version of inverter logic.Keith Rothman2021-03-237-8/+131
* | | Merge pull request #639 from litghost/parameter_iterationgatecat2021-03-235-42/+315
|\| | | |/ |/|
| * Update FPGA interchange chipdb to v4 with inverter data.Keith Rothman2021-03-231-1/+22
| * Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-234-41/+284
| * Update latest version of FPGA interchange schema.Keith Rothman2021-03-231-1/+10
* | Merge pull request #642 from YosysHQ/gatecat/missing-cell-pingatecat2021-03-231-0/+3
|\ \ | |/ |/|
| * interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
* | Initial lookahead for FPGA interchange.Keith Rothman2021-03-2313-13/+2682
|/
* Merge pull request #638 from litghost/fixup_physical_netlist_writergatecat2021-03-221-11/+93
|\
| * Correct some bugs in writing of physical netlist w.r.t. site sources.Keith Rothman2021-03-221-11/+93
* | Merge pull request #637 from litghost/refine_site_routergatecat2021-03-2217-588/+2745
|\ \
| * | Rework FPGA interchange site router.Keith Rothman2021-03-2212-571/+2617
| * | Add missing dependencies to CMake targets.Keith Rothman2021-03-225-17/+128
| |/
* | Merge pull request #634 from litghost/add_get_bel_pin_typegatecat2021-03-221-0/+4
|\ \
| * | Add getBelPinType to Python interface.Keith Rothman2021-03-221-0/+4
| |/
* / Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-222-3/+3
|/
* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-223-6/+143
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-198-891/+1289