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* gowin: fix styleYRabbit2023-04-201-16/+16
* gowin: fix styleYRabbit2023-04-201-1/+1
* gowin: add a common mechanism for placing portsYRabbit2023-04-202-53/+35
* gowin: Remove inherited code for ODDR(c)YRabbit2023-04-144-153/+40
* gowin: Fix styleYRabbit2023-04-121-1/+1
* gowin: implement IDES16 and OSER16 primitivesYRabbit2023-04-125-19/+454
* gowin: Add implementation of IDDR and IDDRC primitivesYRabbit2023-04-062-17/+30
* gowin: Add support for IDES primitivesYRabbit2023-04-043-16/+159
* gowin: bugfixYRabbit2023-03-232-2/+3
* gowin: Rename questionable portsYRabbit2023-03-233-50/+50
* gowin: Change the way errors are processedYRabbit2023-03-231-4/+4
* gowin: Add support for OSER primitivesYRabbit2023-03-236-40/+338
* cmake: Make HeAP placer always-enabledgatecat2023-03-171-9/+1
* gowin: Add bels for new types of oscillatoruis2023-02-062-0/+21
* gowin: Add PLL support for the GW1NS-2C chipYRabbit2023-01-312-1/+8
* gowin: Add PLL support for GW1NR-4 chipsYRabbit2023-01-312-2/+6
* gowin: Proper use of the C++ mechanismsYRabbit2023-01-302-10/+8
* gowin: Add PLL support for the GW1NR-9 chipYRabbit2023-01-303-46/+56
* gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-267-104/+125
* gowin: improve error messageYRabbit2023-01-191-1/+2
* gowin: to use the FB network detection functionYRabbit2023-01-191-0/+6
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-187-38/+202
* gowin: improve clock wire routingYRabbit2022-12-305-45/+69
* gowin: correct the delay calculationYRabbit2022-12-291-5/+16
* gowin: fix build for wasmYRabbit2022-12-213-0/+12
* gowin: not crush on unknown clock tap's sourcesYRabbit2022-12-141-1/+1
* gowin: BUGFIX: Correctly handle resetsYRabbit2022-12-092-13/+14
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-072-2/+2
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| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-072-3/+3
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| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
* | gowin: change the way networks are handledYRabbit2022-12-061-7/+8
* | gowin: add PLL pins processingYRabbit2022-12-045-10/+133
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* gowin: add information about pin configurationsYRabbit2022-11-252-4/+22
* gowin: mark the PLL ports that are not in useYRabbit2022-11-202-0/+16
* gowin: add support for a more common chipYRabbit2022-11-121-1/+1
* gowin: use ctx->idf() a bitYRabbit2022-11-112-41/+17
* gowin: add initial PLL supportYRabbit2022-11-106-1/+227
* run clangformatgatecat2022-10-171-1/+2
* support windows line endingsLushay Labs2022-10-091-4/+4
* gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
* refactor: Use IdString::in instead of || chainsgatecat2022-08-103-6/+4
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-1/+1
* gowin: fix compilationYRabbit2022-07-191-8/+0
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
* gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
* Merge branch 'master' into clock-wipYRabbit2022-07-056-0/+187
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| * use DFF RAM modePepijn de Vos2022-07-021-1/+4
| * Merge branch 'master' into shadowramPepijn de Vos2022-07-025-15/+310
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| * | hook up CE maybePepijn de Vos2022-06-163-0/+4
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