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* Updates from clangformatClifford Wolf2018-06-171-5/+10
* Refactore ice40 chipdb to use a super-large C-string as output formatClifford Wolf2018-06-171-5/+5
* Updates from clangformatClifford Wolf2018-06-171-6/+12
* Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-171-64/+64
* Move PackageInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-1/+1
* Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-3/+3
* Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-171-4/+4
* Progress with chipdb refactoringClifford Wolf2018-06-161-1/+1
* Progress with chipdb refactoringClifford Wolf2018-06-161-2/+2
* Progress with chipdb refactoringClifford Wolf2018-06-161-2/+2
* Merge remote-tracking branch 'origin/master' into chipdbngClifford Wolf2018-06-161-0/+9
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| * ice40: Only place IO at valid pinsDavid Shah2018-06-161-0/+9
* | Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-161-6/+6
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* Refactor position/delay estimation APIClifford Wolf2018-06-141-23/+13
* Add A*-like optimizations to routerClifford Wolf2018-06-131-1/+1
* Add hierarchy to bel/wire/pip namesClifford Wolf2018-06-131-1/+21
* Update chip Graphics APIClifford Wolf2018-06-131-17/+17
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-131-0/+24
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| * ice40: Add a PCF parserDavid Shah2018-06-131-0/+14
| * ice40: Add package selectionDavid Shah2018-06-131-0/+10
* | Redesign PosInfo APIClifford Wolf2018-06-131-9/+23
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* Add fast IdString <-> PortPin conversionClifford Wolf2018-06-121-14/+12
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-121-0/+20
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| * ice40: Adding a placement validity checkerDavid Shah2018-06-121-0/+20
* | Add nextpnr namespaceClifford Wolf2018-06-121-0/+4
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* Add "nextpnr.h"Clifford Wolf2018-06-111-1/+1
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-111-8/+8
* Pass design to gui, display chip nameMiodrag Milanovic2018-06-101-0/+29
* Add support for iCE40 global buffers (currently only for 1k devices)Clifford Wolf2018-06-101-0/+4
* Fix ice40 pip/switch locked performance issueClifford Wolf2018-06-101-1/+1
* ice40: Lock out mutually exclusive pipsDavid Shah2018-06-101-0/+1
* ice40: Writing an empty ASC fileDavid Shah2018-06-101-1/+1
* Getting rid of .nil() methods, compare with zero- and default-constructed obj...Clifford Wolf2018-06-091-6/+6
* Add very basic routerClifford Wolf2018-06-091-12/+23
* ice40: Refactor PortPin and add Python bindingDavid Shah2018-06-071-210/+2
* clang-format for design and chip codebaseClifford Wolf2018-06-071-374/+377
* Add ICE40_HX1K_ONLY config macroClifford Wolf2018-06-071-0/+7
* Add iCE40 device selection, improve iCE40 IO GraphicElementsClifford Wolf2018-06-061-8/+32
* Add ice40 geometry informationClifford Wolf2018-06-061-6/+58
* Refactor Chip API and iCE40 databaseClifford Wolf2018-06-061-10/+86
* Initial JSON parserZipCPU2018-06-051-0/+3
* Add iCE40 blockram belsClifford Wolf2018-06-041-0/+170
* Add iCE40 SB_IO belsClifford Wolf2018-06-031-24/+60
* Add ice40 ICESTORM_LC belsClifford Wolf2018-06-021-6/+24
* Progress in chip.h APIClifford Wolf2018-05-261-4/+64
* Progress in ice40 chipdbClifford Wolf2018-05-261-1/+10
* Start work on iCE40 chipdbClifford Wolf2018-05-261-0/+34
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