aboutsummaryrefslogtreecommitdiffstats
path: root/ice40/chipdb.py
Commit message (Expand)AuthorAgeFilesLines
...
* Deterministic chipdb blobsClifford Wolf2018-07-111-2/+2
* Add opetion to defie ICEBOX_ROOT, fix compile on other locationMiodrag Milanovic2018-07-031-1/+2
* Make chibdb.py able to generate pure binary outputMiodrag Milanovic2018-07-031-5/+27
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-06-221-1/+1
|\
| * Merge branch 'q3k/gl' into 'master'Serge Bazanski2018-06-221-1/+1
| |\
| | * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/glSergiusz Bazanski2018-06-221-4/+66
| | |\
| | * | chipdb.py style fixSergiusz Bazanski2018-06-201-1/+1
* | | | ice40: Adding extra cell wires to database; SB_WARMBOOT workingDavid Shah2018-06-221-0/+47
|/ / /
* | / ice40: Preparations for extra cells supportDavid Shah2018-06-221-0/+12
| |/ |/|
* | ice40: Add UltraPlus tiles to databaseDavid Shah2018-06-221-4/+66
|/
* Improve --tmfuzz mode and iCE40 delay estimatorClifford Wolf2018-06-201-4/+4
* Fix chipdb UltraPlus wiresDavid Shah2018-06-201-1/+1
* Add better iCE40 delay estimatesClifford Wolf2018-06-201-5/+113
* Refactore ice40 chipdb to use a super-large C-string as output formatClifford Wolf2018-06-171-18/+76
* Minor chipdb.py improvementClifford Wolf2018-06-171-2/+17
* Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-171-19/+32
* Move PackageInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-6/+8
* Move TileType array to ice40 chipdb blobClifford Wolf2018-06-171-6/+13
* Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-8/+14
* Move IerenInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-12/+11
* Move TileInfoPOD to chipdb blobClifford Wolf2018-06-171-6/+14
* Move SwitchInfoPOD to chipdb blobClifford Wolf2018-06-171-14/+24
* Move PipInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-6/+28
* Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-26/+48
* Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-171-67/+123
* Progress with chipdb refactoringClifford Wolf2018-06-161-10/+22
* Progress with chipdb refactoringClifford Wolf2018-06-161-39/+34
* Progress with chipdb refactoringClifford Wolf2018-06-161-9/+150
* Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-161-1/+1
* Drastically reduce number of linker symbols in chipdbClifford Wolf2018-06-131-18/+40
* Add missing iCE40 global buffer belsClifford Wolf2018-06-131-0/+18
* Add hierarchy to bel/wire/pip namesClifford Wolf2018-06-131-6/+6
* ice40: Update examples to use packer/pcfDavid Shah2018-06-131-2/+3
* ice40: Add package pins to databaseDavid Shah2018-06-131-2/+36
* Add nextpnr namespaceClifford Wolf2018-06-121-1/+8
* Add "nextpnr.h"Clifford Wolf2018-06-111-1/+1
* Improving 5k supportDavid Shah2018-06-101-2/+11
* Fix iCE40 routing graphClifford Wolf2018-06-101-22/+1
* Add support for iCE40 global buffers (currently only for 1k devices)Clifford Wolf2018-06-101-0/+20
* Debugging on icebreakerDavid Shah2018-06-101-2/+2
* Fix ice40 pip/switch locked performance issueClifford Wolf2018-06-101-1/+1
* ice40: Add IO config to bitstreamDavid Shah2018-06-101-2/+17
* ice40: Adding non-routing config bits to databaseDavid Shah2018-06-101-2/+55
* ice40: Add switch data to databaseDavid Shah2018-06-101-6/+47
* Renamed LOC attribute to BEL, fix ice40 IO bel namesClifford Wolf2018-06-091-1/+1
* Getting rid of .nil() methods, compare with zero- and default-constructed obj...Clifford Wolf2018-06-091-1/+1
* Add very basic routerClifford Wolf2018-06-091-6/+28
* Add ice40 geometry informationClifford Wolf2018-06-061-8/+31
* Refactor Chip API and iCE40 databaseClifford Wolf2018-06-061-35/+54
* Add iCE40 blockram belsClifford Wolf2018-06-041-0/+31
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 21:11:43 +0000