aboutsummaryrefslogtreecommitdiffstats
path: root/ice40/chipdb.py
Commit message (Collapse)AuthorAgeFilesLines
* Use bbasm to create iCE40 chipdbClifford Wolf2018-07-241-273/+38
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-241-37/+1
|\
| * Remove uphill/downhill bel pins from ice40 dbClifford Wolf2018-07-241-30/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-35/+3
| |
* | ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-12/+18
| |
* | ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-241-1/+1
| |
* | ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-0/+41
|/
* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-231-40/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-221-2/+27
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ice40: Add virtual padin wires for intoscs and GB_IOsDavid Shah2018-07-191-1/+14
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Adding data for extra cell configurationDavid Shah2018-07-191-3/+22
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Remove pip names from ice40 chip db to safe memoryClifford Wolf2018-07-151-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 Pip gfxClifford Wolf2018-07-151-6/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40 gfx wire indicesClifford Wolf2018-07-131-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Updates from clang-formatClifford Wolf2018-07-121-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40 wire segments in lutff complexClifford Wolf2018-07-121-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve iCE40 wire database and gfxClifford Wolf2018-07-121-1/+34
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Deterministic chipdb blobsClifford Wolf2018-07-111-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add opetion to defie ICEBOX_ROOT, fix compile on other locationMiodrag Milanovic2018-07-031-1/+2
|
* Make chibdb.py able to generate pure binary outputMiodrag Milanovic2018-07-031-5/+27
|
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-06-221-1/+1
|\
| * Merge branch 'q3k/gl' into 'master'Serge Bazanski2018-06-221-1/+1
| |\ | | | | | | | | | | | | Modern OpenGL renderer See merge request SymbioticEDA/nextpnr!1
| | * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/glSergiusz Bazanski2018-06-221-4/+66
| | |\
| | * | chipdb.py style fixSergiusz Bazanski2018-06-201-1/+1
| | | |
* | | | ice40: Adding extra cell wires to database; SB_WARMBOOT workingDavid Shah2018-06-221-0/+47
|/ / / | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | / ice40: Preparations for extra cells supportDavid Shah2018-06-221-0/+12
| |/ |/| | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Add UltraPlus tiles to databaseDavid Shah2018-06-221-4/+66
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Improve --tmfuzz mode and iCE40 delay estimatorClifford Wolf2018-06-201-4/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix chipdb UltraPlus wiresDavid Shah2018-06-201-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add better iCE40 delay estimatesClifford Wolf2018-06-201-5/+113
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactore ice40 chipdb to use a super-large C-string as output formatClifford Wolf2018-06-171-18/+76
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Minor chipdb.py improvementClifford Wolf2018-06-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-171-19/+32
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move PackageInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-6/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move TileType array to ice40 chipdb blobClifford Wolf2018-06-171-6/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-8/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move IerenInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-12/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move TileInfoPOD to chipdb blobClifford Wolf2018-06-171-6/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move SwitchInfoPOD to chipdb blobClifford Wolf2018-06-171-14/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move PipInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-6/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-26/+48
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-171-67/+123
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Progress with chipdb refactoringClifford Wolf2018-06-161-10/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Progress with chipdb refactoringClifford Wolf2018-06-161-39/+34
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Progress with chipdb refactoringClifford Wolf2018-06-161-9/+150
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Drastically reduce number of linker symbols in chipdbClifford Wolf2018-06-131-18/+40
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add missing iCE40 global buffer belsClifford Wolf2018-06-131-0/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 17:42:44 +0000