| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename getWireBelPin to getBelPinWire | Clifford Wolf | 2018-07-22 | 6 | -18/+18 |
| * | clangformat | Clifford Wolf | 2018-07-22 | 3 | -8/+4 |
| * | Merge branch 'q3k/lock-2-electric-boogaloo' into 'master' | Clifford Wolf | 2018-07-21 | 2 | -4/+12 |
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| | * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Sergiusz Bazanski | 2018-07-21 | 9 | -543/+904 |
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| | * | | Re-enable drawing Pips. | Sergiusz Bazanski | 2018-07-20 | 1 | -3/+3 |
| | * | | clang-format | Sergiusz Bazanski | 2018-07-20 | 1 | -1/+1 |
| | * | | Nuke IdStringDB | Sergiusz Bazanski | 2018-07-20 | 1 | -1/+1 |
| | * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Sergiusz Bazanski | 2018-07-20 | 16 | -95/+361 |
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| | * | | | WIP. | Serge Bazanski | 2018-07-17 | 1 | -0/+8 |
| | * | | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Serge Bazanski | 2018-07-17 | 1 | -4/+4 |
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| | * \ \ \ | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Serge Bazanski | 2018-07-15 | 5 | -14/+261 |
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| | * | | | | | Refactor IdString functionality into IdStringDB | Serge Bazanski | 2018-07-14 | 1 | -1/+1 |
| * | | | | | | Add Loc constructors | Clifford Wolf | 2018-07-21 | 1 | -6/+1 |
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| * | | | | | Added driver and users for nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+8 |
| * | | | | | Merge branch 'router1ng' into 'master' | Clifford Wolf | 2018-07-21 | 1 | -0/+1 |
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| | * | | | | | Refactoring of router1 | Clifford Wolf | 2018-07-21 | 1 | -0/+1 |
| * | | | | | | Map ports to nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+14 |
| * | | | | | | create io cells out of asc | Miodrag Milanovic | 2018-07-21 | 1 | -0/+27 |
| * | | | | | | add cells that are in default state or no configuration | Miodrag Milanovic | 2018-07-21 | 1 | -0/+40 |
| * | | | | | | Add used cells and attach them to bels | Miodrag Milanovic | 2018-07-21 | 1 | -0/+39 |
| * | | | | | | Assign proper pips | Miodrag Milanovic | 2018-07-21 | 1 | -9/+27 |
| * | | | | | | add only missing net | Miodrag Milanovic | 2018-07-21 | 1 | -3/+6 |
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| * | | | | | Change DelayInfo semantics to what we actually need | Clifford Wolf | 2018-07-21 | 1 | -3/+8 |
| * | | | | | Add getWireDelay API | Clifford Wolf | 2018-07-21 | 1 | -0/+6 |
| * | | | | | Fix warnings and status | Miodrag Milanovic | 2018-07-21 | 2 | -2/+19 |
| * | | | | | Made save project work as well | Miodrag Milanovic | 2018-07-21 | 1 | -3/+0 |
| * | | | | | fix introduced bug | Miodrag Milanovic | 2018-07-21 | 1 | -0/+2 |
| * | | | | | Bind wires to net | Miodrag Milanovic | 2018-07-20 | 1 | -629/+637 |
| * | | | | | Add Location APIs to generic arch | Clifford Wolf | 2018-07-20 | 2 | -8/+20 |
| * | | | | | Improve iCE40 and common Loc code | Clifford Wolf | 2018-07-20 | 3 | -15/+33 |
| * | | | | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapi | Clifford Wolf | 2018-07-20 | 18 | -132/+517 |
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| | * | | | | | Few more checks on parameters and error eol | Miodrag Milanovic | 2018-07-20 | 2 | -7/+17 |
| | * | | | | | Start adding bitstream reading for ice40 | Miodrag Milanovic | 2018-07-20 | 3 | -33/+142 |
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| | * | | | | ice40: Optimise reset/enable net checking | David Shah | 2018-07-20 | 3 | -11/+14 |
| | * | | | | ice40: Trim DSP inputs that are constant where appropriate | David Shah | 2018-07-19 | 1 | -0/+4 |
| | * | | | | ice40: Packer and bitstream gen support for MAC16s | David Shah | 2018-07-19 | 3 | -3/+111 |
| | * | | | | ice40: Adding cell definition for DSPs | David Shah | 2018-07-19 | 4 | -5/+79 |
| | * | | | | ice40: Add virtual padin wires for intoscs and GB_IOs | David Shah | 2018-07-19 | 1 | -1/+14 |
| | * | | | | Reducing performance cost of asserts | David Shah | 2018-07-19 | 1 | -1/+1 |
| | * | | | | ice40: Adding data for extra cell configuration | David Shah | 2018-07-19 | 2 | -4/+39 |
| | * | | | | ice40: Renaming | David Shah | 2018-07-18 | 4 | -9/+9 |
| | * | | | | ice40: Fixes for inverted clocks | David Shah | 2018-07-18 | 3 | -2/+7 |
| | * | | | | Cleanups in iCE40 blinky and picorv32 tests | Clifford Wolf | 2018-07-18 | 4 | -35/+2 |
| | * | | | | ice40: Use xArchArgs in validity check | David Shah | 2018-07-18 | 4 | -39/+39 |
| | * | | | | ice40: Make assignArchArgs a Arch method; call also after legaliser | David Shah | 2018-07-18 | 4 | -31/+37 |
| | * | | | | ice40: Assign ArchArgs after packing | David Shah | 2018-07-18 | 7 | -14/+63 |
| | * | | | | Add ArchNetInfo and ArchCellInfo | Clifford Wolf | 2018-07-17 | 1 | -1/+3 |
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| * / | | | Add Loc struct for x/y/z bel locations | Clifford Wolf | 2018-07-17 | 1 | -2/+29 |
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| * | / | refactor: Remove incorrect uses of the term 'wirelength' | David Shah | 2018-07-16 | 1 | -4/+4 |
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| * | | Remove pip names from ice40 chip db to safe memory | Clifford Wolf | 2018-07-15 | 3 | -5/+19 |
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index : iCE40/nextpnr | |
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