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authorJames McKenzie <james.mckenzie@hp.com>2023-05-02 12:22:04 +0100
committerJames McKenzie <james.mckenzie@hp.com>2023-05-02 12:22:04 +0100
commit58bd38ccfd0cde824830a93e309e4f9d8d29ed27 (patch)
tree66d1155f801076ef772368a9eef32a9be8bf41df
parent605179b018fd2d562716cb1880bdc22a441c815d (diff)
downloadtim_ac3rf_fpga_kit-master.tar.gz
tim_ac3rf_fpga_kit-master.tar.bz2
tim_ac3rf_fpga_kit-master.zip
working vhdlHEADmaster
-rw-r--r--.gitignore8
-rw-r--r--.gitmodules6
-rw-r--r--Makefile23
-rw-r--r--src/.gitignore3
m---------src/ghdl0
m---------src/ghdl-yosys-plugin0
-rw-r--r--src/vhdl-demo/.gitignore1
-rw-r--r--src/vhdl-demo/Makefile45
-rw-r--r--src/vhdl-demo/ice40hx8k-evb.pcf5
-rw-r--r--src/vhdl-demo/top.vhd40
10 files changed, 125 insertions, 6 deletions
diff --git a/.gitignore b/.gitignore
index 9f9860a..8160065 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,6 @@
-bin/
-sbin/
-share/
+/bin
+/sbin
+/share
+/include
+/lib
diff --git a/.gitmodules b/.gitmodules
index 5f5cd9c..56456e8 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,9 @@
[submodule "src/flashrom"]
path = src/flashrom
url = git://git.panaceas.org/iCE40/flashrom
+[submodule "src/ghdl"]
+ path = src/ghdl
+ url = git://git.panaceas.org/iCE40/ghdl
+[submodule "src/ghdl-yosys-plugin"]
+ path = src/ghdl-yosys-plugin
+ url = git://git.panaceas.org/iCE40/ghdl-yosys-plugin
diff --git a/Makefile b/Makefile
index bb1159f..c369599 100644
--- a/Makefile
+++ b/Makefile
@@ -1,16 +1,35 @@
PREFIX=${PWD}
-default:src/tools.stamp src/evb-yosys-demo.stamp
+default:src/tools.stamp src/evb-yosys-demo.stamp src/vhdl-demo.stamp
+
+src/vhdl-demo.stamp: src/tools.stamp
+ ${MAKE} -C src/vhdl-demo
+ touch $@
src/evb-yosys-demo.stamp: src/tools.stamp
${MAKE} -C src/evb-yosys-demo/ice40hx8k-evb
${MAKE} -C src/evb-yosys-demo/ice40-io-video
touch $@
-src/tools.stamp: src/nextpnr.stamp src/yosys.stamp src/flashrom.stamp
+src/tools.stamp: src/nextpnr.stamp src/yosys.stamp src/flashrom.stamp src/ghdl-yosys-plugin.stamp src/ghdl.stamp
+ touch $@
+
+
+src/ghdl-yosys-plugin.stamp: src/ghdl.stamp src/yosys.stamp
+ ${MAKE} -C src/ghdl-yosys-plugin GHDL=${PREFIX}/bin/ghdl YOSYS_CONFIG=${PREFIX}/bin/yosys-config
+ ${MAKE} -C src/ghdl-yosys-plugin GHDL=${PREFIX}/bin/ghdl YOSYS_CONFIG=${PREFIX}/bin/yosys-config install
+ touch $@
+
+src/ghdl.stamp: src/ghdl-build/Makefile
+ ${MAKE} -C src/ghdl-build
+ ${MAKE} -C src/ghdl-build install
touch $@
+src/ghdl-build/Makefile:
+ mkdir -p src/ghdl-build
+ (cd src/ghdl-build && ../ghdl/configure --prefix=${PREFIX})
+
src/yosys.stamp:#src/yosys/Makefile
# the muppets did not make this easy
if [ -d src/yosys/abc]; then ln -s ../abc src/yosys/abc; fi
diff --git a/src/.gitignore b/src/.gitignore
index ac5abaf..d41d203 100644
--- a/src/.gitignore
+++ b/src/.gitignore
@@ -1 +1,2 @@
-*.stamp
+/*.stamp
+/ghdl-build
diff --git a/src/ghdl b/src/ghdl
new file mode 160000
+Subproject 635824fbd90bb79d0c0e617bd5457fd1c2c015f
diff --git a/src/ghdl-yosys-plugin b/src/ghdl-yosys-plugin
new file mode 160000
+Subproject 5b64ccfdeee6c75f70487c1ea153ec3e1fb26cd
diff --git a/src/vhdl-demo/.gitignore b/src/vhdl-demo/.gitignore
new file mode 100644
index 0000000..796b96d
--- /dev/null
+++ b/src/vhdl-demo/.gitignore
@@ -0,0 +1 @@
+/build
diff --git a/src/vhdl-demo/Makefile b/src/vhdl-demo/Makefile
new file mode 100644
index 0000000..8a68e1f
--- /dev/null
+++ b/src/vhdl-demo/Makefile
@@ -0,0 +1,45 @@
+PREFIX=../..
+BINDIR=${PREFIX}/bin
+
+YOSYS=${BINDIR}/yosys
+NEXTPNR=${BINDIR}/nextpnr-ice40
+ICEPACK=${BINDIR}/icepack
+ICETIME=${BINDIR}/icetime
+FLASH=${BINDIR}/flash
+GHDL=${BINDIR}/ghdl
+
+BUILDDIR = ./build
+FPGA_TYPE = hx8k
+FPGA_PKG = ct256
+PCF = ice40hx8k-evb.pcf
+RMDIR = rmdir
+
+# Targets
+top: $(BUILDDIR)/top.rpt $(BUILDDIR)/top.bin
+
+flash: $(BUILDDIR)/top.bin
+ ${FLASH} $(BUILDDIR)/top.bin
+
+$(BUILDDIR)/%.json: %.vhd
+ @mkdir -p $(@D)
+ ${YOSYS} -m ghdl -ql $(subst .json,,$@).log -p 'ghdl $< -e ${<:%.vhd=%}; synth_ice40 -abc9 -device u -top top -json $@'
+
+%.asc: %.json
+ ${NEXTPNR} --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@
+
+%.bin: %.asc
+ ${ICEPACK} $< $@
+
+%.rpt: %.asc
+ ${ICETIME} -d $(FPGA_TYPE) -mtr $@ $<
+
+all: top
+
+clean:
+ rm -f $(BUILDDIR)/*.asc $(BUILDDIR)/*.bin $(BUILDDIR)/*.rpt $(BUILDDIR)/*.log $(BUILDDIR)/*.json
+ $(RMDIR) $(BUILDDIR)
+
+# Uncomment this line if you want to keep the intermediate .json and .asc files
+# .PRECIOUS: $(BUILDDIR)/%.json %.asc
+
+.PHONY: all prog clean top
diff --git a/src/vhdl-demo/ice40hx8k-evb.pcf b/src/vhdl-demo/ice40hx8k-evb.pcf
new file mode 100644
index 0000000..43f6208
--- /dev/null
+++ b/src/vhdl-demo/ice40hx8k-evb.pcf
@@ -0,0 +1,5 @@
+set_io CLK100MHZ J3
+set_io btns[0] K11
+set_io btns[1] P13
+set_io leds[0] M12
+set_io leds[1] R16
diff --git a/src/vhdl-demo/top.vhd b/src/vhdl-demo/top.vhd
new file mode 100644
index 0000000..99d0293
--- /dev/null
+++ b/src/vhdl-demo/top.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity top is
+ port (
+ CLK100MHZ: in std_logic;
+
+ -- various stuff defined in the xdc file needs to be defined somewhere
+ leds: out std_logic_vector(1 downto 0);
+ btns: in std_logic_vector(1 downto 0)
+
+ );
+end top;
+
+
+architecture rtl of top is
+ signal led: std_logic;
+begin
+ resetLogic: process (CLK100MHZ)
+ variable i: unsigned(31 downto 0) := to_unsigned(0, 32);
+ begin
+ if rising_edge(CLK100MHZ) then
+ if i >= to_unsigned(100000000, 32) then
+ led <= not led;
+ i := to_unsigned(0,32);
+ else
+ i := i + 1;
+ end if;
+ end if;
+ end process;
+
+ leds(0) <= led;
+ leds(1) <= not led;
+end rtl;
+
+
+
+