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| author | Claire Xen <claire@symbioticeda.com> | 2020-12-01 12:31:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-01 12:31:34 +0100 |
| commit | 7b0cfd5c36af774ae255459d4ef0fa0934929902 (patch) | |
| tree | cf7fce2a15b877ca8fbbaa2dba24c6d35e4814bb /backends/cxxrtl | |
| parent | ef5b2777c3a6e3abaa0aa24012bd47e2a2c8a4db (diff) | |
| parent | c1f6ce8b33b1c06a4e38b621e27876d5715eb26d (diff) | |
| download | yosys-7b0cfd5c36af774ae255459d4ef0fa0934929902.tar.gz yosys-7b0cfd5c36af774ae255459d4ef0fa0934929902.tar.bz2 yosys-7b0cfd5c36af774ae255459d4ef0fa0934929902.zip | |
Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines
Fix SYNTHESIS always being defined in Verilog frontend
Diffstat (limited to 'backends/cxxrtl')
0 files changed, 0 insertions, 0 deletions