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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:19:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:19:11 +0200 |
| commit | 161565be104fd0c7b7c4224bd23e9502625e041a (patch) | |
| tree | f0c54a731d73dc7b334579acb56950497a9e1cb6 /frontends/ast/genrtlil.cc | |
| parent | 5640b7d6078a681e33e85f06920394204f41c875 (diff) | |
| download | yosys-161565be104fd0c7b7c4224bd23e9502625e041a.tar.gz yosys-161565be104fd0c7b7c4224bd23e9502625e041a.tar.bz2 yosys-161565be104fd0c7b7c4224bd23e9502625e041a.zip | |
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 47ca37bd0..2f5370fe8 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -310,6 +310,7 @@ struct AST_INTERNAL::ProcessGenerator case AST_COND: case AST_ALWAYS: + case AST_INITIAL: for (auto child : ast->children) if (child->type == AST_BLOCK) collect_lvalues(reg, child, type_eq, type_le, false); @@ -1013,7 +1014,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) break; // use ProcessGenerator for always blocks - case AST_ALWAYS: { + case AST_ALWAYS: + case AST_INITIAL: { AstNode *always = this->clone(); ProcessGenerator generator(always); delete always; |