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| author | Jannis Harder <me@jix.one> | 2022-05-09 16:07:39 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-09 16:07:39 +0200 |
| commit | 5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd (patch) | |
| tree | fa7a31d02a6de07779a4f7b7934fb662c5efc06d /frontends/verific/verific.h | |
| parent | d562bfd165b3c107abf717d2661c44aa2b7740fb (diff) | |
| parent | 96f64f4788ca64adde55421a6abadefd182d9a1a (diff) | |
| download | yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.tar.gz yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.tar.bz2 yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.zip | |
Merge pull request #3297 from jix/sva_nested_clk_else
verific: Fix conditions of SVAs with explicit clocks within procedures
Diffstat (limited to 'frontends/verific/verific.h')
| -rw-r--r-- | frontends/verific/verific.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 416b26396..695c04f3b 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -44,6 +44,7 @@ struct VerificClocking { SigBit disable_sig = State::S0; bool posedge = true; bool gclk = false; + bool cond_pol = true; VerificClocking() { } VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false); |