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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-05 06:49:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-05 06:49:18 -0700 |
| commit | 7a62ee57b4953a01637086d409a99b9779a7d6c9 (patch) | |
| tree | 65e5a6c22a393ca75421e135bf02e725f45aa9d8 /frontends/verilog/preproc.cc | |
| parent | 99aff5a0f9f322bf4498fe06094de9919ed56681 (diff) | |
| parent | eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37 (diff) | |
| download | yosys-7a62ee57b4953a01637086d409a99b9779a7d6c9.tar.gz yosys-7a62ee57b4953a01637086d409a99b9779a7d6c9.tar.bz2 yosys-7a62ee57b4953a01637086d409a99b9779a7d6c9.zip | |
Merge pull request #2024 from YosysHQ/eddie/primitive_src
verilog: set src attribute for primitives
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions