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| author | gatecat <gatecat@ds0.me> | 2021-05-15 14:34:48 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 22:37:06 +0100 |
| commit | eb106732d94322fb5b48fbff0420ce5a6fc83eb9 (patch) | |
| tree | 3ed44e78ce74793b5d5625c04475641e6e977a33 /techlibs/intel_alm/common/misc_sim.v | |
| parent | 5dba138c87762d4b5bb7b9348da372a92fab1cc0 (diff) | |
| download | yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.tar.gz yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.tar.bz2 yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.zip | |
intel_alm: Add global buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs/intel_alm/common/misc_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/misc_sim.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/misc_sim.v b/techlibs/intel_alm/common/misc_sim.v index e9494a8ee..b1f970a21 100644 --- a/techlibs/intel_alm/common/misc_sim.v +++ b/techlibs/intel_alm/common/misc_sim.v @@ -10,3 +10,12 @@ module MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output assign PAD = OE ? I : 1'bz; assign O = PAD; endmodule + +// Eventually, we should support clock enables and model them here too. +// For now, CLKENA is used as a basic entry point to global routing. +module MISTRAL_CLKBUF ( + input A, + (* clkbuf_driver *) output Q +); + assign Q = A; +endmodule
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