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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-04 15:35:47 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 01:00:29 +0100 |
| commit | 30854b9c7f23e2817a445761022668d6b0f7c0ef (patch) | |
| tree | 83471ee10f31862015bab189c3684ade82e23c47 /techlibs/xilinx/Makefile.inc | |
| parent | 95c46ccc555769cd9d24bae27e0b7264f06e3d66 (diff) | |
| download | yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.gz yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.bz2 yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.zip | |
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 60b4ace1c..7785bf81c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -27,6 +27,9 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sa_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) |