diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 17:26:25 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 17:26:25 -0800 |
| commit | 79db12f238b2f8c5d547ea731a056f98d89bc4b9 (patch) | |
| tree | 777a7b6e595ea9bdc97094380abcbb80b4cacf10 /techlibs/xilinx | |
| parent | 11128dccb53983e7bb784cf2514edcaa6eb822fb (diff) | |
| parent | 04a2eb82045a658de22cea610a3ac8c5dee9333c (diff) | |
| download | yosys-79db12f238b2f8c5d547ea731a056f98d89bc4b9.tar.gz yosys-79db12f238b2f8c5d547ea731a056f98d89bc4b9.tar.bz2 yosys-79db12f238b2f8c5d547ea731a056f98d89bc4b9.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 51d2cbbd2..63d00027a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -556,7 +556,6 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); - abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else |