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| author | tklam <tklam@easylogic.hk> | 2018-10-03 21:17:03 +0800 |
|---|---|---|
| committer | tklam <tklam@easylogic.hk> | 2018-10-03 21:17:03 +0800 |
| commit | 27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12 (patch) | |
| tree | 24b47553fb2aff94f4bd15315f3d43e29db5d30f /techlibs | |
| parent | b86eb3deef7d80fc5450379c80047636832ef458 (diff) | |
| parent | 76baae4b946cdeb04026120b495c87a6146358d0 (diff) | |
| download | yosys-27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12.tar.gz yosys-27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12.tar.bz2 yosys-27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/dram.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt index b3252fa9a..b94357429 100644 --- a/techlibs/ecp5/dram.txt +++ b/techlibs/ecp5/dram.txt @@ -13,4 +13,5 @@ endbram match $__TRELLIS_DPR16X4 make_outreg + min wports 1 endmatch |