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| author | whitequark <whitequark@whitequark.org> | 2021-02-21 20:53:56 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-21 20:53:56 +0000 |
| commit | 3fee43cde0ec424e52ea62f78722b061aaac280a (patch) | |
| tree | c3fe7d79380e9bf2c73c56543f5461715e0a0395 /techlibs | |
| parent | 127484e675538fbaeca1f6e53ba264a1f02e9cf6 (diff) | |
| parent | 220cb1f7bbf6405117b953526c50a21a5ef5788f (diff) | |
| download | yosys-3fee43cde0ec424e52ea62f78722b061aaac280a.tar.gz yosys-3fee43cde0ec424e52ea62f78722b061aaac280a.tar.bz2 yosys-3fee43cde0ec424e52ea62f78722b061aaac280a.zip | |
Merge pull request #2591 from zachjs/verilog-preproc-unapplied
verilog: error on macro invocations with missing argument lists
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions