Merge remote-tracking branch 'origin/master' into xaig_dff

8 files changed, 122 insertions, 124 deletions

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 6049b4225..3aa686e81 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -584,6 +584,50 @@ module FDSE_1 (
 `endif
 endmodule
 
+module LDCE (
+  output reg Q,
+  (* invertible_pin = "IS_CLR_INVERTED" *)
+  input CLR,
+  input D,
+  (* invertible_pin = "IS_G_INVERTED" *)
+  input G,
+  input GE
+);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter [0:0] IS_G_INVERTED = 1'b0;
+  parameter MSGON = "TRUE";
+  parameter XON = "TRUE";
+  initial Q = INIT;
+  wire clr = CLR ^ IS_CLR_INVERTED;
+  wire g = G ^ IS_G_INVERTED;
+  always @*
+    if (clr) Q = 1'b0;
+    else if (GE && g) Q = D;
+endmodule
+
+module LDPE (
+  output reg Q,
+  input D,
+  (* invertible_pin = "IS_G_INVERTED" *)
+  input G,
+  input GE,
+  (* invertible_pin = "IS_PRE_INVERTED" *)
+  input PRE
+);
+  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] IS_G_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter MSGON = "TRUE";
+  parameter XON = "TRUE";
+  initial Q = INIT;
+  wire g = G ^ IS_G_INVERTED;
+  wire pre = PRE ^ IS_PRE_INVERTED;
+  always @*
+    if (pre) Q = 1'b1;
+    else if (GE && g) Q = D;
+endmodule
+
 module RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
   (* abc_arrival=1153 *)
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 561a61943..13dbc0e14 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -108,8 +108,8 @@ XC6S_CELLS = [
     # Cell('FDRE'),
     # Cell('FDSE'),
     Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
-    Cell('LDCE'),
-    Cell('LDPE'),
+    # Cell('LDCE'),
+    # Cell('LDPE'),
     Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
 
     # Slice/CLB primitives.
diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v
index 014e73df0..f8dcce81d 100644
--- a/techlibs/xilinx/xc6s_cells_xtra.v
+++ b/techlibs/xilinx/xc6s_cells_xtra.v
@@ -1793,36 +1793,6 @@ module IDDR2 (...);
     input S;
 endmodule
 
-module LDCE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-endmodule
-
-module LDPE (...);
-    parameter [0:0] INIT = 1'b1;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
 module ODDR2 (...);
     parameter DDR_ALIGNMENT = "NONE";
     parameter [0:0] INIT = 1'b0;
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v
index 520a67579..bf35b09e5 100644
--- a/techlibs/xilinx/xc6s_ff_map.v
+++ b/techlibs/xilinx/xc6s_ff_map.v
@@ -18,7 +18,12 @@
  */
 
 // ============================================================================
-// FF mapping
+// FF mapping for Spartan 6.  The primitives used are the same as Series 7,
+// but with one major difference: the initial value is implied by the
+// primitive type used (FFs with reset pin must have INIT set to 0 or x, FFs
+// with set pin must have INIT set to 1 or x).  For Yosys primitives without
+// set/reset, this means we have to pick the primitive type based on the INIT
+// value.
 
 `ifndef _NO_FFS
 
@@ -29,6 +34,7 @@ module  \$_DFF_N_   (input D, C, output Q);
   else
     FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_P_   (input D, C, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -37,6 +43,7 @@ module  \$_DFF_P_   (input D, C, output Q);
   else
     FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 module  \$_DFFE_NP_ (input D, C, E, output Q);
@@ -46,6 +53,7 @@ module  \$_DFFE_NP_ (input D, C, E, output Q);
   else
     FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -54,6 +62,7 @@ module  \$_DFFE_PP_ (input D, C, E, output Q);
   else
     FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 module  \$_DFF_NN0_ (input D, C, R, output Q);
@@ -63,6 +72,7 @@ module  \$_DFF_NN0_ (input D, C, R, output Q);
   else
     FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_NP0_ (input D, C, R, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -71,6 +81,7 @@ module  \$_DFF_NP0_ (input D, C, R, output Q);
   else
     FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PN0_ (input D, C, R, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -79,6 +90,7 @@ module  \$_DFF_PN0_ (input D, C, R, output Q);
   else
     FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -87,6 +99,7 @@ module  \$_DFF_PP0_ (input D, C, R, output Q);
   else
     FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 module  \$_DFF_NN1_ (input D, C, R, output Q);
@@ -96,6 +109,7 @@ module  \$_DFF_NN1_ (input D, C, R, output Q);
   else
     FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_NP1_ (input D, C, R, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -104,6 +118,7 @@ module  \$_DFF_NP1_ (input D, C, R, output Q);
   else
     FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PN1_ (input D, C, R, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -112,6 +127,7 @@ module  \$_DFF_PN1_ (input D, C, R, output Q);
   else
     FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -120,6 +136,26 @@ module  \$_DFF_PP1_ (input D, C, R, output Q);
   else
     FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
   endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module  \$_DLATCH_N_ (input E, D, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0));
+  else
+    LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
+  endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module  \$_DLATCH_P_ (input E, D, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0));
+  else
+    LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
+  endgenerate
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 `endif
diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v
index 263bcc69d..b228e404d 100644
--- a/techlibs/xilinx/xc6v_cells_xtra.v
+++ b/techlibs/xilinx/xc6v_cells_xtra.v
@@ -2648,36 +2648,6 @@ module IDDR_2CLK (...);
     input S;
 endmodule
 
-module LDCE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-endmodule
-
-module LDPE (...);
-    parameter [0:0] INIT = 1'b1;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
 module ODDR (...);
     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
     parameter INIT = 1'b0;
diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v
index 817932e9f..0d16f81c3 100644
--- a/techlibs/xilinx/xc7_cells_xtra.v
+++ b/techlibs/xilinx/xc7_cells_xtra.v
@@ -5149,36 +5149,6 @@ module IDDR_2CLK (...);
     input S;
 endmodule
 
-module LDCE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-endmodule
-
-module LDPE (...);
-    parameter [0:0] INIT = 1'b1;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
 module ODDR (...);
     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
     parameter INIT = 1'b0;
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
index f6197b78b..32ca9f560 100644
--- a/techlibs/xilinx/xc7_ff_map.v
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -18,60 +18,98 @@
  */
 
 // ============================================================================
-// FF mapping
+// FF mapping for Virtex 6, Series 7 and Ultrascale.  These families support
+// the following features:
+//
+// - a CLB flip-flop can be used as a latch or as a flip-flop
+// - a CLB flip-flop has the following pins:
+//
+//   - data input
+//   - clock (or gate for latches) (with optional inversion)
+//   - clock enable (or gate enable, which is just ANDed with gate — unused by
+//     synthesis)
+//   - either a set or a reset input, which (for FFs) can be either
+//     synchronous or asynchronous (with optional inversion)
+//   - data output
+//
+// - a flip-flop also has an initial value, which is set at device
+//   initialization (or whenever GSR is asserted)
 
 `ifndef _NO_FFS
 
 module  \$_DFF_N_   (input D, C, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_P_   (input D, C, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 module  \$_DFFE_NP_ (input D, C, E, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 module  \$_DFF_NN0_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_NP0_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PN0_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 module  \$_DFF_NN1_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_NP1_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PN1_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module  \$_DLATCH_N_ (input E, D, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module  \$_DLATCH_P_ (input E, D, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  LDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
+  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 `endif
diff --git a/techlibs/xilinx/xcu_cells_xtra.v b/techlibs/xilinx/xcu_cells_xtra.v
index 2d331a221..4523b5210 100644
--- a/techlibs/xilinx/xcu_cells_xtra.v
+++ b/techlibs/xilinx/xcu_cells_xtra.v
@@ -10731,36 +10731,6 @@ module IDDRE1 (...);
     input R;
 endmodule
 
-module LDCE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-endmodule
-
-module LDPE (...);
-    parameter [0:0] INIT = 1'b1;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
 module ODDRE1 (...);
     parameter [0:0] IS_C_INVERTED = 1'b0;
     parameter [0:0] IS_D1_INVERTED = 1'b0;