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| author | Jannis Harder <me@jix.one> | 2022-05-31 15:56:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-31 15:56:36 +0200 |
| commit | 01cb02c81df14762cce117a823af742ed044a5c4 (patch) | |
| tree | e766145cefa1dc2acf65be28fc0f12e9d0c51e49 /tests/verilog/func_tern_hint.ys | |
| parent | a79a228c2ba3259a1d8783f69990acd10e0efb5a (diff) | |
| parent | a650d9079fa4732a6d118f2764d5abc2522a6b37 (diff) | |
| download | yosys-01cb02c81df14762cce117a823af742ed044a5c4.tar.gz yosys-01cb02c81df14762cce117a823af742ed044a5c4.tar.bz2 yosys-01cb02c81df14762cce117a823af742ed044a5c4.zip | |
Merge pull request #3348 from zachjs/func-tern-hint
verilog: fix width/sign detection for functions
Diffstat (limited to 'tests/verilog/func_tern_hint.ys')
| -rw-r--r-- | tests/verilog/func_tern_hint.ys | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/verilog/func_tern_hint.ys b/tests/verilog/func_tern_hint.ys new file mode 100644 index 000000000..ab8a1e032 --- /dev/null +++ b/tests/verilog/func_tern_hint.ys @@ -0,0 +1,4 @@ +read_verilog -sv func_tern_hint.sv +proc +opt +sat -verify -seq 1 -prove-asserts -show-all |