20 files changed, 345 insertions, 25 deletions

diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v
new file mode 100644
index 000000000..704ca3fda
--- /dev/null
+++ b/tests/simple/arraycells.v
@@ -0,0 +1,15 @@
+
+module array_test001(a, b, c, y);
+	input a;
+	input [31:0] b, c;
+	input [31:0] y;
+
+	aoi12 p [31:0] (a, b, c, y);
+endmodule
+
+module aoi12(a, b, c, y);
+	input a, b, c;
+	output y;
+	assign y = ~((a & b) | c);
+endmodule
+
diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v
index 70ee7e667..8b7aa279d 100644
--- a/tests/simple/forgen01.v
+++ b/tests/simple/forgen01.v
@@ -1,3 +1,6 @@
+
+// VERIFIC-SKIP
+
 module uut_forgen01(a, y);
 
 input [4:0] a;
diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v
index 79ca041dd..2dba14bb0 100644
--- a/tests/simple/fsm.v
+++ b/tests/simple/fsm.v
@@ -1,7 +1,7 @@
 
 // `define ASYNC_RESET
 
-module test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
+module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
 
 input clk, reset, button_a, button_b;
 output reg red_a, green_a, red_b, green_b;
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 39e573a73..24eb4462c 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -1,5 +1,5 @@
 
-module test1(clk, a, b, y);
+module gen_test1(clk, a, b, y);
 
 input clk;
 input [7:0] a, b;
@@ -40,7 +40,7 @@ endmodule
 
 // ------------------------------------------
 
-module test2(clk, a, b, y);
+module gen_test2(clk, a, b, y);
 
 input clk;
 input [7:0] a, b;
@@ -67,7 +67,7 @@ endmodule
 
 // ------------------------------------------
 
-module test3(a, b, sel, y, z);
+module gen_test3(a, b, sel, y, z);
 
 input [3:0] a, b;
 input sel;
diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v
index f8f564085..3aa596632 100644
--- a/tests/simple/i2c_master_tests.v
+++ b/tests/simple/i2c_master_tests.v
@@ -3,7 +3,7 @@
 // this core that triggered bugs in early versions of yosys.
 
 // from i2c_master_bit_ctrl
-module test01(clk, rst, nReset, al);
+module i2c_test01(clk, rst, nReset, al);
 
 	input clk, rst, nReset;
 	output reg al;
@@ -26,7 +26,7 @@ module test01(clk, rst, nReset, al);
 endmodule
 
 // from i2c_master_bit_ctrl
-module test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
+module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
 
 	input clk, slave_wait, clk_cnt;
 	input cmd;
diff --git a/tests/simple/macros.v b/tests/simple/macros.v
index cda46cb48..7b4d616ea 100644
--- a/tests/simple/macros.v
+++ b/tests/simple/macros.v
@@ -235,3 +235,10 @@ always @* begin
 end
 
 endmodule
+
+`define SIZE 4 // comment supported in this part
+module test_comment_in_macro ( din_a, dout_a );
+input [`SIZE-1:0] din_a;
+output [`SIZE-1:0] dout_a;
+assign dout_a = din_a | `SIZE'ha;
+endmodule
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index e2c136ddb..bed5528d4 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -1,5 +1,5 @@
 
-module test1(in_addr, in_data, out_addr, out_data);
+module mem2reg_test1(in_addr, in_data, out_addr, out_data);
 
 input [1:0] in_addr, out_addr;
 input [3:0] in_data;
@@ -19,7 +19,7 @@ endmodule
 
 // ------------------------------------------------------
 
-module test2(clk, mode, addr, data);
+module mem2reg_test2(clk, mode, addr, data);
 
 input clk, mode;
 input [2:0] addr;
@@ -43,3 +43,15 @@ end
 
 endmodule
 
+// ------------------------------------------------------
+
+// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
+module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
+reg [7:0] dint_c [0:7]; 
+always @(posedge clk)
+  begin
+      {dout_a[0], dint_c[3]} <= din_a;
+  end
+assign dout_b = dint_c[3];
+endmodule
+
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v
index 4022f57cd..9bd38fcb3 100644
--- a/tests/simple/mem_arst.v
+++ b/tests/simple/mem_arst.v
@@ -10,7 +10,7 @@ module MyMem #(
   output [DataWidth-1:0] Data_o,
   input                  WR_i);
 
-  reg Data_o;
+  reg [DataWidth-1:0] Data_o;
 
   localparam Size = 2**AddrWidth;
 
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index 927ee0438..db06c56d2 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -1,5 +1,5 @@
 
-module test00(clk, setA, setB, y);
+module memtest00(clk, setA, setB, y);
 
 input clk, setA, setB;
 output y;
@@ -16,7 +16,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
+module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
 
 input clk, wr_en;
 input [3:0] wr_addr, rd_addr;
@@ -36,7 +36,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
+module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
 
 input clk, setA, setB;
 input [1:0] addr;
@@ -77,7 +77,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
 
 input clk, wr_enable;
 input [3:0] wr_addr, wr_data, rd_addr;
@@ -95,7 +95,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
 
 input clk, wr_enable;
 input [3:0] wr_addr, wr_data, rd_addr;
@@ -114,3 +114,94 @@ assign rd_data = memory[rd_addr_buf];
 
 endmodule
 
+// ----------------------------------------------------------
+
+module memtest05(clk, addr, wdata, rdata, wen);
+
+input clk;
+input [1:0] addr;
+input [7:0] wdata;
+output reg [7:0] rdata;
+input [3:0] wen;
+
+reg [7:0] mem [0:3];
+
+integer i;
+always @(posedge clk) begin
+	for (i = 0; i < 4; i = i+1)
+		if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
+	rdata <= mem[addr];
+end
+
+endmodule
+
+// ----------------------------------------------------------
+
+module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+    (* gentb_constant=0 *) wire rst;
+    reg [7:0] test [0:7];
+    integer i;
+    always @(posedge clk) begin
+        if (rst) begin
+            for (i=0; i<8; i=i+1)
+                test[i] <= 0;
+        end else begin
+            test[0][2] <= din[1];
+            test[0][5] <= test[0][2];
+            test[idx][3] <= din[idx];
+            test[idx][6] <= test[idx][2];
+            test[idx][idx] <= !test[idx][idx];
+        end
+    end
+    assign dout = test[idx];
+endmodule
+
+module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+    (* gentb_constant=0 *) wire rst;
+    reg [7:0] test [0:7];
+    integer i;
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            for (i=0; i<8; i=i+1)
+                test[i] <= 0;
+        end else begin
+            test[0][2] <= din[1];
+            test[0][5] <= test[0][2];
+            test[idx][3] <= din[idx];
+            test[idx][6] <= test[idx][2];
+            test[idx][idx] <= !test[idx][idx];
+        end
+    end
+    assign dout = test[idx];
+endmodule
+
+// ----------------------------------------------------------
+
+module memtest07(clk, addr, woffset, wdata, rdata);
+
+input clk;
+input [1:0] addr;
+input [3:0] wdata;
+input [1:0] woffset;
+output reg [7:0] rdata;
+
+reg [7:0] mem [0:3];
+
+integer i;
+always @(posedge clk) begin
+	mem[addr][woffset +: 4] <= wdata;
+	rdata <= mem[addr];
+end
+
+endmodule
+
+// ----------------------------------------------------------
+
+module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y);
+	reg [3:0] mem [0:15] [0:15];
+	always @(posedge clk) begin
+		y <= mem[a][b];
+		mem[a][b] <= c;
+	end
+endmodule
+
diff --git a/tests/simple/operators.v b/tests/simple/operators.v
index 7439101c8..2f0fdb820 100644
--- a/tests/simple/operators.v
+++ b/tests/simple/operators.v
@@ -1,4 +1,4 @@
-module test(clk, mode, u1, s1, u2, s2, y);
+module optest(clk, mode, u1, s1, u2, s2, y);
 
 input clk;
 input [6:0] mode;
diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v
index 8d0134a67..23cb276f2 100644
--- a/tests/simple/paramods.v
+++ b/tests/simple/paramods.v
@@ -1,5 +1,5 @@
 
-module test1(a, b, x, y);
+module pm_test1(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
@@ -11,7 +11,7 @@ endmodule
 
 // -----------------------------------
 
-module test2(a, b, x, y);
+module pm_test2(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
@@ -23,7 +23,7 @@ endmodule
 
 // -----------------------------------
 
-module test3(a, b, x, y);
+module pm_test3(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index acfc1ca5d..7461358ad 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -1,5 +1,62 @@
-module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
+module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
 wire [5:0] offset = idx << 2;
 assign slice_up = data[offset +: 4];
 assign slice_down = data[offset + 3 -: 4];
 endmodule
+
+module partsel_test002 (
+	input clk, rst,
+	input [7:0] a,
+	input [0:7] b,
+	input [1:0] s,
+	output [7:0] x1, x2, x3,
+	output [0:7] x4, x5, x6,
+	output [7:0] y1, y2, y3,
+	output [0:7] y4, y5, y6,
+	output [7:0] z1, z2, z3,
+	output [0:7] z4, z5, z6,
+	output [7:0] w1, w2, w3,
+	output [0:7] w4, w5, w6,
+	output [7:0] p1, p2, p3, p4, p5, p6,
+	output [0:7] q1, q2, q3, q4, q5, q6,
+	output reg [7:0] r1,
+	output reg [0:7] r2
+);
+
+assign x1 = a, x2 = a + b, x3 = b;
+assign x4 = a, x5 = a + b, x6 = b;
+assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];
+assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];
+assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];
+assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];
+assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];
+assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];
+assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];
+assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];
+
+always @(posedge clk) begin
+	if (rst) begin
+		{ r1, r2 } = 16'h1337 ^ {a, b};
+	end else begin
+		case (s)
+			0: begin
+				r1[3:0] <= r2[0:3] ^ x1;
+				r2[4:7] <= r1[7:4] ^ x4;
+			end
+			1: begin
+				r1[2 +: 3] <= r2[5 -: 3] + x1;
+				r2[3 +: 3] <= r1[6 -: 3] + x4;
+			end
+			2: begin
+				r1[6 -: 3] <= r2[3 +: 3] - x1;
+				r2[7 -: 3] <= r1[4 +: 3] - x4;
+			end
+			3: begin
+				r1 <= r2;
+				r2 <= r1;
+			end
+		endcase
+	end
+end
+
+endmodule
diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v
new file mode 100644
index 000000000..5b756e6be
--- /dev/null
+++ b/tests/simple/realexpr.v
@@ -0,0 +1,24 @@
+
+module demo_001(y1, y2, y3, y4);
+	output [7:0] y1, y2, y3, y4;
+
+	localparam [7:0] p1 = 123.45;
+	localparam real p2 = 123.45;
+	localparam real p3 = 123;
+	localparam p4 = 123.45;
+
+	assign y1 = p1 + 0.2;
+	assign y2 = p2 + 0.2;
+	assign y3 = p3 + 0.2;
+	assign y4 = p4 + 0.2;
+endmodule
+
+module demo_002(y0, y1, y2, y3);
+	output [63:0] y0, y1, y2, y3;
+
+	assign y0 = 1'bx >= (-1 * -1.17);
+	assign y1 = 1 ?  1 ?  -1 : 'd0 : 0.0;
+	assign y2 = 1 ? -1 :   1 ? 'd0 : 0.0;
+	assign y3 = 1 ? -1 : 'd0;
+endmodule
+
diff --git a/tests/simple/repwhile.v b/tests/simple/repwhile.v
new file mode 100644
index 000000000..5d0c75fa6
--- /dev/null
+++ b/tests/simple/repwhile.v
@@ -0,0 +1,36 @@
+module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x);
+
+	function [7:0] mylog2;
+		input [31:0] value;
+		begin
+			mylog2 = 0;
+			while (value > 0) begin
+				value = value >> 1;
+				mylog2 = mylog2 + 1;
+			end
+		end
+	endfunction
+
+	function [31:0] myexp2;
+		input [7:0] value;
+		begin
+			myexp2 = 1;
+			repeat (value)
+				myexp2 = myexp2 << 1;
+		end
+	endfunction
+
+	reg [7:0] y_table [63:0];
+	reg [31:0] x_table [63:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 64; i = i+1) begin
+			y_table[i] <= mylog2(i);
+			x_table[i] <= myexp2(i);
+		end
+	end
+
+	assign y = y_table[a];
+	assign x = x_table[a];
+endmodule
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index eb6fd10ba..6531d51ae 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -6,5 +6,4 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-make -C ../.. || exit 1
-exec bash ../tools/autotest.sh *.v
+exec ${MAKE:-make} -f ../tools/autotest.mk *.v
diff --git a/tests/simple/scopes.v b/tests/simple/scopes.v
new file mode 100644
index 000000000..eecc1a0b2
--- /dev/null
+++ b/tests/simple/scopes.v
@@ -0,0 +1,63 @@
+module scopes_test_01(input [3:0] k, output reg [15:0] x, y);
+	function [15:0] func_01;
+		input [15:0] x, y;
+		begin
+			func_01 = x + y;
+			begin:blk
+				reg [15:0] x;
+				x = y;
+				func_01 = func_01 ^ x;
+			end
+			func_01 = func_01 ^ x;
+		end
+	endfunction
+
+	function [15:0] func_02;
+		input [15:0] x, y;
+		begin
+			func_02 = x - y;
+			begin:blk
+				reg [15:0] func_02;
+				func_02 = 0;
+			end
+		end
+	endfunction
+
+	task task_01;
+		input [3:0] a;
+		reg [15:0] y;
+		begin
+			y = a * 23;
+			x = x + y;
+		end
+	endtask
+
+	task task_02;
+		input [3:0] a;
+		begin:foo
+			reg [15:0] x, z;
+			x = y;
+			begin:bar
+				reg [15:0] x;
+				x = 77 + a;
+				z = -x;
+			end
+			y = x ^ z;
+		end
+	endtask
+
+	always @* begin
+		x = func_01(11, 22);
+		y = func_02(33, 44);
+		task_01(k);
+		task_02(k);
+		begin:foo
+			reg [15:0] y;
+			y = x;
+			y = y + k;
+			x = y;
+		end
+		x = func_01(y, x);
+		y = func_02(y, x);
+	end
+endmodule
diff --git a/tests/simple/signedexpr.v b/tests/simple/signedexpr.v
index 3eb5e93df..8bba4a4b1 100644
--- a/tests/simple/signedexpr.v
+++ b/tests/simple/signedexpr.v
@@ -1,4 +1,4 @@
-module test01(a, b, xu, xs, yu, ys, zu, zs);
+module signed_test01(a, b, xu, xs, yu, ys, zu, zs);
 
 input signed [1:0] a;
 input signed [2:0] b;
diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index 3a09cbc35..51e31015f 100644
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -1,5 +1,5 @@
 
-module test01(clk, a, b, c, x, y, z, w);
+module task_func_test01(clk, a, b, c, x, y, z, w);
 
 input clk;
 input [7:0] a, b, c;
@@ -33,3 +33,16 @@ end
 
 endmodule
 
+
+module task_func_test02( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a);
+	assign dout_a = test(din_a,din_b);
+	function [7:0] test;
+		input [7:0] a;
+		input [7:0] b;
+		begin : TEST
+			integer i;
+			for (i = 0; i <= 7; i = i + 1)
+				test[i] = a[i] & b[i];
+		end
+	endfunction
+endmodule
diff --git a/tests/simple/undef_eqx_nex.v b/tests/simple/undef_eqx_nex.v
index 63912a2fa..b0178677b 100644
--- a/tests/simple/undef_eqx_nex.v
+++ b/tests/simple/undef_eqx_nex.v
@@ -1,4 +1,4 @@
-module test(y);
+module undef_eqx_nex(y);
 output [7:0] y;
 assign y[0] = 0/0;
 assign y[1] = 0/1;
diff --git a/tests/simple/usb_phy_tetsts.v b/tests/simple/usb_phy_tests.v
index 2375183d8..bc45e71a5 100644
--- a/tests/simple/usb_phy_tetsts.v
+++ b/tests/simple/usb_phy_tests.v
@@ -1,6 +1,6 @@
 
 // from usb_rx_phy
-module test01(clk, rst, rx_en, fs_ce);
+module usb_phy_test01(clk, rst, rx_en, fs_ce);
 
 input		clk, rst;
 input		rx_en;