| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #712 from mmicko/anlogic-support | Clifford Wolf | 2018-12-05 | 7 | -0/+1278 |
| |\ | | | | | Initial support for Anlogic FPGA | ||||
| | * | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 |
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| | * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 7 | -0/+1590 |
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| * | | Rename opt_lut.cpp to opt_lut.cc | Clifford Wolf | 2018-12-05 | 1 | -0/+0 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #717 from whitequark/opt_lut | Clifford Wolf | 2018-12-05 | 9 | -2/+537 |
| |\ \ | | | | | | | Add a new opt_lut pass, which combines inefficiently packed LUTs | ||||
| | * | | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 3 | -20/+166 |
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| | * | | opt_lut: always prefer to eliminate 1-LUTs. | whitequark | 2018-12-05 | 1 | -19/+41 |
| | | | | | | | | | | | | | | | | These are always either buffers or inverters, and keeping the larger LUT preserves more source-level information about the design. | ||||
| | * | | opt_lut: collect and display statistics. | whitequark | 2018-12-05 | 1 | -4/+33 |
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| | * | | opt_lut: refactor to use a worker. NFC. | whitequark | 2018-12-05 | 1 | -170/+177 |
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| | * | | synth_ice40: add -relut option, to run ice40_unlut and opt_lut. | whitequark | 2018-12-05 | 1 | -1/+13 |
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| | * | | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 8 | -1/+320 |
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| * | | | Merge pull request #716 from whitequark/ice40_unlut | Clifford Wolf | 2018-12-05 | 3 | -13/+109 |
| |\| | | | | | | | | Extract ice40_unlut pass from ice40_opt | ||||
| | * | | Extract ice40_unlut pass from ice40_opt. | whitequark | 2018-12-05 | 3 | -13/+109 |
| |/ / | | | | | | | | | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut. | ||||
| * | | Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osx | Serge Bazanski | 2018-12-05 | 2 | -3/+2 |
| |\ \ | | | | | | | Fix Travis on OSX | ||||
| | * | | travis/osx: fix, use clang instead of gcc | Sergiusz Bazanski | 2018-12-05 | 2 | -3/+2 |
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| * | | Fix typo | Clifford Wolf | 2018-12-04 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #702 from smunaut/min_ce_use | Clifford Wolf | 2018-12-04 | 2 | -1/+50 |
| |\ \ | |/ |/| | Add option to only use DFFE is the resulting E signal would be use > N times | ||||
| | * | ice40: Add option to only use CE if it'd be use by more than X FFs | Sylvain Munaut | 2018-11-27 | 1 | -0/+14 |
| | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| | * | dff2dffe: Add option for unmap to only remove DFFE with low CE signal use | Sylvain Munaut | 2018-11-27 | 1 | -1/+36 |
| | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | Merge pull request #676 from rafaeltp/master | Clifford Wolf | 2018-12-01 | 1 | -10/+17 |
| |\ \ | | | | | | | Splits SigSpec into bits before calling check_signal_in_fanout (solves #675) | ||||
| | * | | using [i] to access individual bits of SigSpec and merging bits into a tmp ↵ | rafaeltp | 2018-10-21 | 1 | -11/+12 |
| | | | | | | | | | | | | | Sig before setting the port to new signal | ||||
| | * | | cleaning up for PR | rafaeltp | 2018-10-20 | 2 | -6/+2 |
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| | * | | fixing code style | rafaeltp | 2018-10-20 | 1 | -1/+1 |
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| | * | | solves #675 | rafaeltp | 2018-10-20 | 2 | -11/+21 |
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| | * | | Merge pull request #1 from YosysHQ/master | rafaeltp | 2018-10-20 | 20 | -89/+869 |
| | |\ \ | | | | | | | | | updating | ||||
| * | | | | Improve ConstEval error handling for non-eval cell types | Clifford Wolf | 2018-11-29 | 2 | -9/+19 |
| | |_|/ |/| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Add iteration limit to "opt_muxtree" | Clifford Wolf | 2018-11-20 | 1 | -1/+17 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Update ABC to git rev 2ddc57d | Clifford Wolf | 2018-11-13 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Add "write_aiger -I -O -B" | Clifford Wolf | 2018-11-12 | 1 | -2/+36 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge branch 'master' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-11-12 | 4 | -1/+1044 |
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| | * \ \ | Merge pull request #697 from eddiehung/xilinx_ps7 | Clifford Wolf | 2018-11-12 | 2 | -0/+624 |
| | |\ \ \ | | | | | | | | | | | Add support for PS7 block for Xilinx | ||||
| | | * | | | Add support for Xilinx PS7 block | Eddie Hung | 2018-11-10 | 2 | -0/+624 |
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| | * | | | | Merge pull request #695 from daveshah1/ecp5_bb | Clifford Wolf | 2018-11-12 | 2 | -1/+420 |
| | |\ \ \ \ | | |/ / / | |/| | | | ecp5: Adding some blackbox cells | ||||
| | | * | | | ecp5: Add 'fake' DCU parameters | David Shah | 2018-11-09 | 1 | -0/+11 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | | * | | | ecp5: Add blackboxes for ancillary DCU cells | David Shah | 2018-11-09 | 1 | -0/+18 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | | * | | | ecp5: Adding some blackbox cells | David Shah | 2018-11-07 | 2 | -1/+391 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | | Update ABC to git rev 68da3cf | Clifford Wolf | 2018-11-11 | 1 | -1/+1 |
| |/ / / / | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Merge pull request #696 from arjenroodselaar/verific_darwin | Clifford Wolf | 2018-11-09 | 1 | -0/+4 |
| |\ \ \ \ | | | | | | | | | | | Use appropriate static libraries when building with Verific on MacOS | ||||
| | * | | | | Use appropriate static libraries when building with Verific on MacOS | Arjen Roodselaar | 2018-11-07 | 1 | -0/+4 |
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| * | | | | | Fix "make ystests" to use correct Yosys binary | Clifford Wolf | 2018-11-08 | 1 | -1/+1 |
| |/ / / / | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Merge pull request #693 from YosysHQ/rlimit | Clifford Wolf | 2018-11-07 | 1 | -8/+11 |
| |\ \ \ \ | | | | | | | | | | | improve rlimit handling in smtio.py | ||||
| | * | | | | Limit stack size to 16 MB on Darwin | Clifford Wolf | 2018-11-07 | 1 | -1/+4 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | Fix for improved smtio.py rlimit code | Clifford Wolf | 2018-11-06 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | Improve stack rlimit code in smtio.py | Clifford Wolf | 2018-11-06 | 1 | -8/+8 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | Merge pull request #694 from trcwm/dffmap_expr_fix | Clifford Wolf | 2018-11-06 | 1 | -1/+10 |
| |\ \ \ \ \ | | | | | | | | | | | | | DFFLIBMAP: changed 'missing pin' error into a warning. | ||||
| | * | | | | | DFFLIBMAP: changed 'missing pin' error into a warning with additional ↵ | Niels Moseley | 2018-11-06 | 1 | -1/+10 |
| |/ / / / / | | | | | | | | | | | | | | | | reason/info. | ||||
| * | | | | | Run solver in non-incremental mode whem smtio.py is configured for ↵ | Clifford Wolf | 2018-11-06 | 1 | -3/+12 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | non-incremental solving Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | Update ABC rev to 4d56acf | Clifford Wolf | 2018-11-06 | 1 | -1/+1 |
| |/ / / / | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Allow square brackets in liberty identifiers | Clifford Wolf | 2018-11-05 | 2 | -3/+4 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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