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* ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #1004 from YosysHQ/clifford/fix1002Clifford Wolf2019-05-121-3/+11
|\ | | | | Fix handling of glob_abort_cnt in opt_muxtree
| * Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002Clifford Wolf2019-05-121-3/+11
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1003 from makaimann/zinit-allClifford Wolf2019-05-111-1/+1
|\ | | | | Zinit option '-singleton' -> '-all'
| * Zinit option '-singleton' -> '-all'Makai Mann2019-05-101-1/+1
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* | Add "fmcombine -initeq -anyeq"Clifford Wolf2019-05-111-3/+38
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "stat -tech xilinx"Clifford Wolf2019-05-112-4/+74
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1000 from bwidawsk/synth-formatClifford Wolf2019-05-092-222/+224
|\ | | | | Add clang format, and use on intel_synth (v2)
| * Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | | | | | | | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * Add a .clang-formatBen Widawsky2019-05-091-0/+13
|/ | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Add $stop to documentationClifford Wolf2019-05-091-3/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove added newline (by re-running minisat 00_UPDATE.sh)Clifford Wolf2019-05-081-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-085-5/+9
|\ | | | | Fix all warnings that occurred when compiling with gcc9
| * Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-085-5/+9
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* | Merge pull request #998 from mdaiter/get_bool_attribute_optsClifford Wolf2019-05-081-4/+8
|\ \ | | | | | | Minor optimization to get_attribute_bool
| * | Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
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* | | Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #996 from mdaiter/ceil_log2_optsClifford Wolf2019-05-072-3/+5
|\ \ \ | | | | | | | | Optimize ceil_log2 function
| * | | Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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* | | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | More opt_clean cleanupsClifford Wolf2019-05-071-26/+36
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-0619-51/+810
|\ \ | | | | | | Add specify parser
| * | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "real" keyword to ilang formatClifford Wolf2019-05-063-2/+12
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-063-12/+32
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| * | | Improve write_verilog specify supportClifford Wolf2019-05-043-16/+75
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Update READMEClifford Wolf2019-05-041-5/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | More testingEddie Hung2019-05-032-2/+5
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| * | | Fix spacingEddie Hung2019-05-031-6/+6
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| * | | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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| * | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-0340-405/+931
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| * | | | Add specify support to READMEClifford Wolf2019-04-231-0/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Improve $specrule interfaceClifford Wolf2019-04-234-13/+23
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Improve $specrule interfaceClifford Wolf2019-04-233-24/+24
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-239-6/+133
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Preserve $specify[23] cellsClifford Wolf2019-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-234-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-232-0/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add specify parserClifford Wolf2019-04-235-33/+253
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-063-13/+66
|\ \ \ \ \ | | | | | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| * \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-0635-290/+787
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| * | | | | | Further improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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