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* Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
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* Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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* Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Revert "ABC to call retime all the time"Eddie Hung2019-12-301-11/+15
| | | | This reverts commit 9aa94370a54c016421740d2ce32ef0aa338d0dbd.
* Merge pull request #1599 from YosysHQ/eddie/retry_1588Eddie Hung2019-12-304-20/+87
|\ | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
| * Add #1598 testcaseEddie Hung2019-12-273-0/+48
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| * write_xaiger: inherit port ordering from original moduleEddie Hung2019-12-271-5/+16
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| * Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"Eddie Hung2019-12-271-19/+27
| | | | | | | | | | This reverts commit 92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing changes made to 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804.
* | Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5Eddie Hung2019-12-303-14/+6
|\ \ | |/ |/| Nitpick cleanup for ecp5
| * Update resource countEddie Hung2019-12-281-3/+3
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| * Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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* Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-271-27/+19
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| * Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanupDavid Shah2019-12-271-27/+19
| |\ | | | | | | Revert "write_xaiger: only instantiate each whitebox cell type once"
| | * Revert "write_xaiger: only instantiate each whitebox cell type once"David Shah2019-12-271-27/+19
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* / write_xaiger: simplify c{i,o}_bitsEddie Hung2019-12-271-12/+6
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* fixed invalid charMiodrag Milanovic2019-12-251-1/+1
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* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-252-23/+91
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* Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-2512-81/+1136
|\ | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| * Minor nit fixesMarcin Kościelnicki2019-12-251-2/+2
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| * Add DSP cascade testsEddie Hung2019-12-231-0/+89
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| * Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG tooEddie Hung2019-12-231-8/+18
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| * Fix CEA/CEB checkEddie Hung2019-12-231-2/+2
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| * Fix checking CE[AB] and for direct connectionsEddie Hung2019-12-231-18/+40
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| * Support unregistered cascades for A and B inputsEddie Hung2019-12-231-47/+74
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| * Add DSP48A* PCOUT -> PCIN cascade supportEddie Hung2019-12-231-10/+10
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| * xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-2210-14/+921
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* | xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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* Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-201-19/+27
|\ | | | | write_xaiger: only instantiate each whitebox cell type once
| * write_xaiger: only instantiate each whitebox cell type onceEddie Hung2019-12-201-19/+27
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* | Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
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* | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
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* | Put specify/endspecify inside ``Eddie Hung2019-12-201-4/+4
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* | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lutEddie Hung2019-12-201-19/+18
|\ \ | |/ |/| Interpret "abc9 -lut" as lut string only if [0-9:]
| * Interpret "abc9 -lut" as lut string only if [0-9:]Eddie Hung2019-12-181-19/+18
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* | Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanupEddie Hung2019-12-204-39/+21
|\ \ | | | | | | Revert "Optimise write_xaiger"
| * | Revert "Optimise write_xaiger"Eddie Hung2019-12-204-39/+21
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* | Fix linking with Python 3.8Graham Edgecombe2019-12-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The behaviour of python-config --libs has changed in Python 3.8. For example, compare the output of it with Python 3.7 and 3.8 on an ArchLinux system: $ python3.7-config --libs -lpython3.7m -lcrypt -lpthread -ldl -lutil -lm $ python3.8-config --libs -lcrypt -lpthread -ldl -lutil -lm -lm $ The lack of -lpython in the latter case causes the linker to fail when attempting to build Yosys against Python 3.8. Passing the new --embed flag to python-config adds -lpython, just like earlier versions of Python: $ python3.8-config --embed --libs -lpython3.8 -lcrypt -lpthread -ldl -lutil -lm -lm $ This commit adds code for automatically detecting support for the --embed flag. If it is supported, it is passed to all python-config invocations. This fixes building against Python 3.8.
* | Add PYTHON_CONFIG variable to the MakefileGraham Edgecombe2019-12-201-17/+18
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* | Merge pull request #1581 from YosysHQ/clifford/fix1565Eddie Hung2019-12-191-1/+1
|\ \ | | | | | | Fix sim for assignments with lhs<rhs size
| * | Fix sim for assignments with lhs<rhs size, fixes #1565Clifford Wolf2019-12-171-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-194-21/+39
|\ \ \ | | | | | | | | Optimise write_xaiger
| * | | Stray newlineEddie Hung2019-12-061-1/+0
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| * | | write_xaiger to inst each cell type once, do not call techmap/aigmapEddie Hung2019-12-061-21/+25
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| * | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
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* | | | Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-192-0/+50
|\ \ \ \ | | | | | | | | | | verilog: preserve size of $genval$-s in for loops
| * | | | Stray log_dumpEddie Hung2019-12-111-1/+0
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| * | | | Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
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| * | | | Add testcaseEddie Hung2019-12-111-0/+34
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* | | | | Merge pull request #1571 from YosysHQ/eddie/fix_1570Eddie Hung2019-12-191-3/+1
|\ \ \ \ \ | | | | | | | | | | | | mem_arst.v: do not redeclare ANSI port
| * | | | | Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
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