iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Add minimal support for PSL in VHDL via Verific	Clifford Wolf	2017-07-28	1	-19/+155
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*	Add simple VHDL+PSL example	Clifford Wolf	2017-07-28	4	-17/+64
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*	Improve Verific HDL language options	Clifford Wolf	2017-07-28	1	-4/+4
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*	Fix handling of non-user-declared Verific netbus	Clifford Wolf	2017-07-28	1	-2/+3
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*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	2	-7/+42
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*	Add counter.sv SVA test	Clifford Wolf	2017-07-27	1	-0/+29
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*	Add log_warning_noprefix() API, Use for Verific warnings and errors	Clifford Wolf	2017-07-27	3	-1/+37
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*	Add "verific -import -n" and "verific -import -nosva"	Clifford Wolf	2017-07-27	1	-14/+36
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*	Improve SVA tests, add Makefile and scripts	Clifford Wolf	2017-07-27	11	-9/+110
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*	Improve Verific SVA import: negedge and $past	Clifford Wolf	2017-07-27	1	-6/+49
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*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	1	-37/+58
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*	Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ↵	Clifford Wolf	2017-07-26	1	-0/+47
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*	Improve Verific bindings (mostly related to SVA)	Clifford Wolf	2017-07-26	1	-110/+320
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*	Improve "help verific" message	Clifford Wolf	2017-07-25	1	-5/+5
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*	Add "verific -extnets"	Clifford Wolf	2017-07-25	1	-23/+130
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*	Add "using std::get" to yosys.h	Clifford Wolf	2017-07-25	1	-0/+1
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*	Improve "verific -all" handling	Clifford Wolf	2017-07-25	1	-26/+45
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*	Add "verific -import -d <dump_file"	Clifford Wolf	2017-07-24	1	-6/+35
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*	Add "verific -import -flatten" and "verific -import -v"	Clifford Wolf	2017-07-24	1	-107/+164
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*	Add more SVA test cases for future Verific work	Clifford Wolf	2017-07-22	5	-1/+74
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*	Add "verific -import -k"	Clifford Wolf	2017-07-22	1	-42/+51
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*	Add error for cell output ports that are connected to constants	Clifford Wolf	2017-07-22	1	-20/+21
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*	Add some simple SVA test cases for future Verific work	Clifford Wolf	2017-07-22	4	-0/+45
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*	Improve docs for verific bindings, add simply sby example	Clifford Wolf	2017-07-22	5	-48/+89
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*	Fix handling of empty cell port assignments (i.e. ignore them)	Clifford Wolf	2017-07-21	2	-0/+6
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*	Fix "read_blif -wideports" handling of cells with wide ports	Clifford Wolf	2017-07-21	1	-3/+33
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*	Add a paragraph about pre-defined macros to read_verilog help message	Clifford Wolf	2017-07-21	1	-0/+4
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*	Add verilator support to testbenches generated by yosys-smtbmc	Clifford Wolf	2017-07-21	1	-3/+15
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*	Change intptr_t to uintptr_t in hashlib.h	Clifford Wolf	2017-07-18	1	-1/+1
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*	Merge pull request #363 from rqou/master	Clifford Wolf	2017-07-18	2	-1/+6
\|\ \| \| \| \|	Miscellaneous build tweaks
\| *	makefile: Add the option to use libtermcap	Robert Ou	2017-07-17	1	-0/+5
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\| *	Fix build warnings for win64	Robert Ou	2017-07-17	1	-1/+1
\|/ \| \| \|	Win64 has a 32-bit long. Use intptr_t to work on any data model.
*	Add $alu to list of supported cells for "stat -width"	Clifford Wolf	2017-07-14	1	-1/+1
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*	Generate FSM-style testbenches in smtbmc	Clifford Wolf	2017-07-12	1	-5/+23
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*	Fix the fixed handling of x-bits in EDIF back-end	Clifford Wolf	2017-07-11	1	-1/+0
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*	Fix handling of x-bits in EDIF back-end	Clifford Wolf	2017-07-11	1	-1/+11
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*	Add attributes and parameter support to JSON front-end	Clifford Wolf	2017-07-10	2	-7/+52
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*	Add techlibs/xilinx/lut2lut.v	Clifford Wolf	2017-07-10	2	-0/+66
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*	Add JSON front-end	Clifford Wolf	2017-07-08	2	-0/+472
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*	Change s/asserts/assertions/ in yosys-smtbmc log messages	Clifford Wolf	2017-07-07	1	-2/+2
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*	Add "yosys-smtbmc --presat"	Clifford Wolf	2017-07-07	1	-3/+23
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*	Fix generation of multiple outputs for same AIG node in write_aiger	Clifford Wolf	2017-07-05	1	-13/+30
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*	Add write_table command	Clifford Wolf	2017-07-05	2	-0/+123
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*	Add Verific Release information to log	Clifford Wolf	2017-07-04	1	-0/+12
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*	Fix some c++ clang compiler errors	Clifford Wolf	2017-07-03	1	-3/+3
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*	Apply minor coding style changes to coolrunner2 target	Clifford Wolf	2017-07-03	2	-1/+1
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*	Merge pull request #352 from rqou/master	Clifford Wolf	2017-07-03	6	-0/+645
\|\ \| \| \| \|	Initial Coolrunner-II support
\| *	coolrunner2: Add a few more primitives	Robert Ou	2017-06-25	1	-0/+110
\| \| \| \| \| \| \| \|	These cannot be inferred yet, but add them to cells_sim.v for now
\| *	coolrunner2: Initial mapping of latches	Robert Ou	2017-06-25	4	-0/+63
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\| *	coolrunner2: Initial mapping of DFFs	Robert Ou	2017-06-25	4	-0/+76
\| \| \| \| \| \| \| \| \| \|	All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)