| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-12-27 | 1 | -27/+19 |
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| | * | Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup | David Shah | 2019-12-27 | 1 | -27/+19 |
| | |\ | | | | | | | Revert "write_xaiger: only instantiate each whitebox cell type once" | ||||
| | | * | Revert "write_xaiger: only instantiate each whitebox cell type once" | David Shah | 2019-12-27 | 1 | -27/+19 |
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| * / | write_xaiger: simplify c{i,o}_bits | Eddie Hung | 2019-12-27 | 1 | -12/+6 |
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| * | fixed invalid char | Miodrag Milanovic | 2019-12-25 | 1 | -1/+1 |
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| * | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 2 | -23/+91 |
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| * | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen | Marcin Kościelnicki | 2019-12-25 | 12 | -81/+1136 |
| |\ | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | ||||
| | * | Minor nit fixes | Marcin Kościelnicki | 2019-12-25 | 1 | -2/+2 |
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| | * | Add DSP cascade tests | Eddie Hung | 2019-12-23 | 1 | -0/+89 |
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| | * | Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too | Eddie Hung | 2019-12-23 | 1 | -8/+18 |
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| | * | Fix CEA/CEB check | Eddie Hung | 2019-12-23 | 1 | -2/+2 |
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| | * | Fix checking CE[AB] and for direct connections | Eddie Hung | 2019-12-23 | 1 | -18/+40 |
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| | * | Support unregistered cascades for A and B inputs | Eddie Hung | 2019-12-23 | 1 | -47/+74 |
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| | * | Add DSP48A* PCOUT -> PCIN cascade support | Eddie Hung | 2019-12-23 | 1 | -10/+10 |
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| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 10 | -14/+921 |
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| * | | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 5 | -7/+362 |
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| * | Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-20 | 1 | -19/+27 |
| |\ | | | | | write_xaiger: only instantiate each whitebox cell type once | ||||
| | * | write_xaiger: only instantiate each whitebox cell type once | Eddie Hung | 2019-12-20 | 1 | -19/+27 |
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| * | | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| * | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 |
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| * | | Put specify/endspecify inside `` | Eddie Hung | 2019-12-20 | 1 | -4/+4 |
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| * | | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut | Eddie Hung | 2019-12-20 | 1 | -19/+18 |
| |\ \ | |/ |/| | Interpret "abc9 -lut" as lut string only if [0-9:] | ||||
| | * | Interpret "abc9 -lut" as lut string only if [0-9:] | Eddie Hung | 2019-12-18 | 1 | -19/+18 |
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| * | | Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup | Eddie Hung | 2019-12-20 | 4 | -39/+21 |
| |\ \ | | | | | | | Revert "Optimise write_xaiger" | ||||
| | * | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 4 | -39/+21 |
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| * | | Fix linking with Python 3.8 | Graham Edgecombe | 2019-12-20 | 1 | -0/+7 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The behaviour of python-config --libs has changed in Python 3.8. For example, compare the output of it with Python 3.7 and 3.8 on an ArchLinux system: $ python3.7-config --libs -lpython3.7m -lcrypt -lpthread -ldl -lutil -lm $ python3.8-config --libs -lcrypt -lpthread -ldl -lutil -lm -lm $ The lack of -lpython in the latter case causes the linker to fail when attempting to build Yosys against Python 3.8. Passing the new --embed flag to python-config adds -lpython, just like earlier versions of Python: $ python3.8-config --embed --libs -lpython3.8 -lcrypt -lpthread -ldl -lutil -lm -lm $ This commit adds code for automatically detecting support for the --embed flag. If it is supported, it is passed to all python-config invocations. This fixes building against Python 3.8. | ||||
| * | | Add PYTHON_CONFIG variable to the Makefile | Graham Edgecombe | 2019-12-20 | 1 | -17/+18 |
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| * | | Merge pull request #1581 from YosysHQ/clifford/fix1565 | Eddie Hung | 2019-12-19 | 1 | -1/+1 |
| |\ \ | | | | | | | Fix sim for assignments with lhs<rhs size | ||||
| | * | | Fix sim for assignments with lhs<rhs size, fixes #1565 | Clifford Wolf | 2019-12-17 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 4 | -21/+39 |
| |\ \ \ | | | | | | | | | Optimise write_xaiger | ||||
| | * | | | Stray newline | Eddie Hung | 2019-12-06 | 1 | -1/+0 |
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| | * | | | write_xaiger to inst each cell type once, do not call techmap/aigmap | Eddie Hung | 2019-12-06 | 1 | -21/+25 |
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| | * | | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 3 | -0/+15 |
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| * | | | | Merge pull request #1569 from YosysHQ/eddie/fix_1531 | Eddie Hung | 2019-12-19 | 2 | -0/+50 |
| |\ \ \ \ | | | | | | | | | | | verilog: preserve size of $genval$-s in for loops | ||||
| | * | | | | Stray log_dump | Eddie Hung | 2019-12-11 | 1 | -1/+0 |
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| | * | | | | Preserve size of $genval$-s in for loops | Eddie Hung | 2019-12-11 | 1 | -0/+17 |
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| | * | | | | Add testcase | Eddie Hung | 2019-12-11 | 1 | -0/+34 |
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| * | | | | | Merge pull request #1571 from YosysHQ/eddie/fix_1570 | Eddie Hung | 2019-12-19 | 1 | -3/+1 |
| |\ \ \ \ \ | | | | | | | | | | | | | mem_arst.v: do not redeclare ANSI port | ||||
| | * | | | | | Make SV2017 compliant courtesy of @wsnyder | Eddie Hung | 2019-12-12 | 1 | -3/+1 |
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| * | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 3 | -156/+210 |
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| * | | | | | | xilinx_dffopt: Keep order of LUT inputs. | Marcin Kościelnicki | 2019-12-19 | 1 | -16/+30 |
| | |_|_|_|/ |/| | | | | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549 | ||||
| * | | | | | Add "scratchpad" to CHANGELOG | Eddie Hung | 2019-12-18 | 1 | -0/+1 |
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| * | | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-12-18 | 24 | -84/+1071 |
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| | * \ \ \ \ | Merge pull request #1563 from YosysHQ/dave/async-prld | David Shah | 2019-12-18 | 2 | -4/+28 |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs | ||||
| | | * | | | | | ecp5: Add support for mapping PRLD FFs | David Shah | 2019-12-07 | 2 | -4/+28 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | | | | Merge pull request #1572 from nakengelhardt/scratchpad_pass | Eddie Hung | 2019-12-18 | 3 | -0/+136 |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | add a command to read/modify scratchpad contents | ||||
| | | * | | | | | | use extra_args | N. Engelhardt | 2019-12-18 | 1 | -1/+1 |
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| | | * | | | | | | add assert option to scratchpad command | N. Engelhardt | 2019-12-16 | 3 | -19/+49 |
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| | | * | | | | | | add periods and newlines to help message | N. Engelhardt | 2019-12-13 | 1 | -5/+5 |
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| | | * | | | | | | add test and make help message more verbose | N. Engelhardt | 2019-12-12 | 2 | -1/+20 |
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