| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | machxo2: Add experimental status to help. | William D. Jones | 2021-02-23 | 1 | -1/+1 | |
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| * | | | | machxo2: Add DCCA and DCMA blackbox primitives. | William D. Jones | 2021-02-23 | 1 | -0/+17 | |
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| * | | | | machxo2: Fix reversed interpretation of REG_SD config bits. | William D. Jones | 2021-02-23 | 1 | -2/+2 | |
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| * | | | | machxo2: Tristate is active-low. | William D. Jones | 2021-02-23 | 2 | -5/+5 | |
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| * | | | | machxo2: Fix typos in FACADE_FF sim model. | William D. Jones | 2021-02-23 | 1 | -5/+4 | |
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| * | | | | machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. | William D. Jones | 2021-02-23 | 2 | -6/+6 | |
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| * | | | | machxo2: Improve help_mode output in synth_machxo2. | William D. Jones | 2021-02-23 | 1 | -5/+5 | |
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| * | | | | machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires ↵ | William D. Jones | 2021-02-23 | 2 | -1/+17 | |
| | | | | | | | | | | | | | | | | | to IO cells. | |||||
| * | | | | machxo2: Add missing OSCH oscillator primitive. | William D. Jones | 2021-02-23 | 1 | -0/+10 | |
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| * | | | | machxo2: Add believed-to-be-correct tribuf test. | William D. Jones | 2021-02-23 | 1 | -0/+9 | |
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| * | | | | machxo2: Add passing fsm, mux, and shifter tests. | William D. Jones | 2021-02-23 | 3 | -0/+65 | |
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| * | | | | machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. | William D. Jones | 2021-02-23 | 3 | -3/+11 | |
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| * | | | | machxo2: Add -noiopad option to synth_machxo2. | William D. Jones | 2021-02-23 | 1 | -2/+11 | |
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| * | | | | machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. | William D. Jones | 2021-02-23 | 1 | -1/+1 | |
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| * | | | | machxo2: Fix cells_sim typo where OFX1 was multiply-driven. | William D. Jones | 2021-02-23 | 1 | -1/+1 | |
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| * | | | | machxo2: synth_machxo2 now maps ports to FACADE_IO. | William D. Jones | 2021-02-23 | 2 | -0/+12 | |
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| * | | | | machxo2: Add initial value for Q in FACADE_FF. | William D. Jones | 2021-02-23 | 1 | -0/+2 | |
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| * | | | | machxo2: Add FACADE_IO simulation model. More comments on models. | William D. Jones | 2021-02-23 | 1 | -0/+25 | |
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| * | | | | machxo2: Add FACADE_SLICE simulation model. | William D. Jones | 2021-02-23 | 1 | -0/+83 | |
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| * | | | | machxo2: Improve FACADE_FF simulation model. | William D. Jones | 2021-02-23 | 1 | -12/+20 | |
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| * | | | | machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. | William D. Jones | 2021-02-23 | 2 | -4/+4 | |
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| * | | | | machxo2: Add dffe test. | William D. Jones | 2021-02-23 | 1 | -0/+9 | |
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| * | | | | machxo2: Add dff.ys test, fix another cells_map.v typo. | William D. Jones | 2021-02-23 | 2 | -1/+11 | |
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| * | | | | machxo2: Fix more oversights in machxo2 models. logic.ys test passes. | William D. Jones | 2021-02-23 | 2 | -2/+6 | |
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| * | | | | machxo2: Add test/arch/machxo2 directory (test does not pass). | William D. Jones | 2021-02-23 | 4 | -0/+15 | |
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| * | | | | machxo2: Fix typos. test/arch/run-test.sh passes. | William D. Jones | 2021-02-23 | 2 | -2/+2 | |
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| * | | | | machxo2: Create basic techlibs and synth_machxo2 pass. | William D. Jones | 2021-02-23 | 4 | -0/+320 | |
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| * | | | | frontend: json: parse negative values | Karol Gugala | 2021-02-23 | 1 | -2/+10 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Karol Gugala <kgugala@antmicro.com> | |||||
| * | | | | assertpmux: Fix crash on unused $pmux output. | Marcelina Kościelnicka | 2021-02-22 | 2 | -1/+19 | |
| | | | | | | | | | | | | | | | | | Fixes #2595. | |||||
| * | | | | Merge pull request #2586 from zachjs/tern-recurse | whitequark | 2021-02-21 | 5 | -19/+195 | |
| |\ \ \ \ | | | | | | | | | | | verilog: support recursive functions using ternary expressions | |||||
| | * | | | | verilog: support recursive functions using ternary expressions | Zachary Snow | 2021-02-12 | 5 | -19/+195 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls. | |||||
| * | | | | | Merge pull request #2591 from zachjs/verilog-preproc-unapplied | whitequark | 2021-02-21 | 3 | -1/+32 | |
| |\ \ \ \ \ | |_|/ / / |/| | | | | verilog: error on macro invocations with missing argument lists | |||||
| | * | | | | verilog: error on macro invocations with missing argument lists | Zachary Snow | 2021-02-19 | 3 | -1/+32 | |
| |/ / / / | | | | | | | | | | | | | | | | | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation. | |||||
| * | | | | Bump version | Yosys Bot | 2021-02-18 | 1 | -1/+1 | |
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| * | | | | Merge pull request #2590 from RobertBaruch/fix_fast_sop_mode | Claire Xen | 2021-02-17 | 1 | -1/+1 | |
| |\ \ \ \ | | | | | | | | | | | Fixes command line for abc pass in -fast -sop mode | |||||
| | * | | | | Fixes command line for abc pass in -fast -sop mode | Robert Baruch | 2021-02-16 | 1 | -1/+1 | |
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| * | | | | Bump version | Yosys Bot | 2021-02-16 | 1 | -1/+1 | |
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| * | | | | Merge pull request #2574 from dh73/master | Claire Xen | 2021-02-15 | 1 | -0/+5 | |
| |\ \ \ \ | | | | | | | | | | | Accept disable case for SVA liveness properties. | |||||
| | * | | | | Accept disable case for SVA liveness properties. | Diego H | 2021-02-04 | 1 | -0/+5 | |
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| * | | | | | Bump version | Yosys Bot | 2021-02-13 | 1 | -1/+1 | |
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| * | | | | Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct | gatecat | 2021-02-12 | 1 | -0/+115 | |
| |\ \ \ \ | | | | | | | | | | | nexus: Add MULTADDSUB9X9WIDE sim model | |||||
| | * | | | | nexus: Add MULTADDSUB9X9WIDE sim model | David Shah | 2020-12-08 | 1 | -0/+115 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | Ganulate Verific support | Miodrag Milanovic | 2021-02-12 | 1 | -8/+16 | |
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| * | | | | | Bump version | Yosys Bot | 2021-02-12 | 1 | -1/+1 | |
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| * | | | | | Merge pull request #2573 from zachjs/repeat-call | whitequark | 2021-02-11 | 4 | -72/+176 | |
| |\ \ \ \ \ | | | | | | | | | | | | | verilog: refactored constant function evaluation | |||||
| | * | | | | | verilog: refactored constant function evaluation | Zachary Snow | 2021-02-04 | 4 | -72/+176 | |
| | | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed. | |||||
| * | | | | | Merge pull request #2578 from zachjs/genblk-port | Zachary Snow | 2021-02-11 | 3 | -4/+29 | |
| |\ \ \ \ \ | | | | | | | | | | | | | verlog: allow shadowing module ports within generate blocks | |||||
| | * | | | | | verlog: allow shadowing module ports within generate blocks | Zachary Snow | 2021-02-07 | 3 | -4/+29 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs. | |||||
| * | | | | | | Merge pull request #2584 from antmicro/atom_type_signedness | Zachary Snow | 2021-02-11 | 2 | -4/+23 | |
| |\ \ \ \ \ \ | |/ / / / / |/| | | | | | verilog_parser: fix missing is_signed attribute in type_atom | |||||
| | * | | | | | Add missing is_signed to type_atom | Kamil Rakoczy | 2021-02-11 | 2 | -4/+23 | |
| |/ / / / / | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
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index : iCE40/yosys | |
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