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* Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-192-0/+50
|\ | | | | verilog: preserve size of $genval$-s in for loops
| * Stray log_dumpEddie Hung2019-12-111-1/+0
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| * Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
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| * Add testcaseEddie Hung2019-12-111-0/+34
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* | Merge pull request #1571 from YosysHQ/eddie/fix_1570Eddie Hung2019-12-191-3/+1
|\ \ | | | | | | mem_arst.v: do not redeclare ANSI port
| * | Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
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* | | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
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* | | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | | Add "scratchpad" to CHANGELOGEddie Hung2019-12-181-0/+1
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* | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-1824-84/+1071
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| * \ \ Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
| |\ \ \ | | | | | | | | | | ecp5: Add support for mapping PRLD FFs
| | * | | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | Merge pull request #1572 from nakengelhardt/scratchpad_passEddie Hung2019-12-183-0/+136
| |\ \ \ \ | | | | | | | | | | | | add a command to read/modify scratchpad contents
| | * | | | use extra_argsN. Engelhardt2019-12-181-1/+1
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| | * | | | add assert option to scratchpad commandN. Engelhardt2019-12-163-19/+49
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| | * | | | add periods and newlines to help messageN. Engelhardt2019-12-131-5/+5
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| | * | | | add test and make help message more verboseN. Engelhardt2019-12-122-1/+20
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| | * | | | add a command to read/modify scratchpad contentsN. Engelhardt2019-12-122-0/+87
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| * | | | Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-testEddie Hung2019-12-181-2/+4
| |\ \ \ \ | | | | | | | | | | | | tests/xilinx: fix flaky mux test
| | * | | | tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
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| * | | | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-1811-27/+638
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| * | | | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-188-49/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| * | | | Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | CleanupEddie Hung2019-12-171-11/+7
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* | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-1613-65/+529
|\ \ \ \ | | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| * \ \ \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
| |\ \ \ \ | | | | | | | | | | | | | | | | | | eddie/xilinx_lutram
| | * | | | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
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| * | | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| * | | | Disable RAM16X1D testEddie Hung2019-12-131-17/+17
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| * | | | Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| * | | | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| * | | | Remove extraneous synth_xilinx callEddie Hung2019-12-121-2/+0
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| * | | | Add tests for these new modelsEddie Hung2019-12-121-0/+40
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| * | | | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| * | | | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| * | | | Add #1460 testcaseEddie Hung2019-12-121-0/+34
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| * | | | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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| * | | | Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-129-53/+156
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* | | | | Merge pull request #1521 from dh73/diego/memattrEddie Hung2019-12-167-48/+374
|\ \ \ \ \ | | | | | | | | | | | | Adding support for Xilinx memory attribute 'block' in single port mode.
| * | | | | Enforce non-existenceEddie Hung2019-12-161-0/+4
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| * | | | | Update docEddie Hung2019-12-161-4/+6
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| * | | | | Add another testEddie Hung2019-12-161-1/+8
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| * | | | | More sloppiness, thanks @dh73 for spottingEddie Hung2019-12-161-4/+4
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| * | | | | Accidentally commented out testsEddie Hung2019-12-161-47/+47
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| * | | | | Add unconditional match blocks for force RAMEddie Hung2019-12-162-4/+45
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| * | | | | OopsEddie Hung2019-12-161-4/+1
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| * | | | | Merge blockram testsEddie Hung2019-12-163-47/+81
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| * | | | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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| * | | | | Implement 'attributes' grammarEddie Hung2019-12-161-80/+88
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| * | | | | Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattrEddie Hung2019-12-164-1/+238
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