iCE40/yosys - [no description]

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* \| \|	Merge pull request #2171 from whitequark/cxxrtl-accessors	whitequark	2020-06-19	1	-6/+47
\|\ \ \ \| \| \| \| \| \| \| \|	cxxrtl: add .get() and .set() accessors on value<> and wire<>
\| * \| \|	cxxrtl: add .get() and .set() accessors on value<> and wire<>.	whitequark	2020-06-19	1	-6/+47
\| \|/ / \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	For several reasons: * They're more convenient than accessing .data. * They accommodate variably-sized types like size_t transparently. * They statically ensure that no out of range conversions happen. For now these are only provided for unsigned integers, but eventually they should be provided for signed integers too. (Annoyingly this affects conversions to/from `char` at the moment.) Fixes #2127.
* \| \|	Merge pull request #2170 from boqwxp/cutpoint-efficiency	whitequark	2020-06-19	1	-9/+10
\|\ \ \ \| \|/ / \|/\| \|	cutpoint: Improve efficiency by iterating over module ports instead of module wires
\| * \|	cutpoint: Improve efficiency by iterating over module ports instead of ↵	Alberto Gonzalez	2020-06-18	1	-9/+10
\|/ / \| \| \| \| \| \|	module wires.
* \|	Merge pull request #2153 from boqwxp/splitnets-cleanup	N. Engelhardt	2020-06-18	1	-16/+19
\|\ \ \| \| \| \| \| \|	splitnets: Cleanup and efficiency improvements
\| * \|	splitnets: Clean up pseudo-private member usage	Alberto Gonzalez	2020-06-13	1	-7/+6
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\| * \|	splitnets: Slightly improve efficiency by avoiding some unnecessary lookups	Alberto Gonzalez	2020-06-13	1	-9/+13
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* \| \|	Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug	whitequark	2020-06-18	1	-1/+2
\|\ \ \ \| \| \| \| \| \| \| \|	cxxrtl: don't compute vital values in log_assert()
\| * \| \|	cxxrtl: don't compute vital values in log_assert().	whitequark	2020-06-17	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This breaks NDEBUG builds. Fixes #2166.
* \| \| \|	Merge pull request #2142 from whitequark/splitnets-hdlname	whitequark	2020-06-18	1	-0/+4
\|\ \ \ \ \| \| \|/ / \| \|/\| \|	splitnets: propagate (hdlname) and disambiguate via start_offset
\| * \| \|	splitnets: propagate (hdlname) and disambiguate via start_offset.	whitequark	2020-06-10	1	-0/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This allows reliably coalescing the split wires later.
* \| \| \|	Merge pull request #2164 from madebr/msvc	Miodrag Milanović	2020-06-18	4	-11/+11
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	Get yosys building on Visual Studio
\| * \| \| \|	msvc does not support designated initializers in structs	Anonymous Maarten	2020-06-17	1	-5/+5
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\| * \| \| \|	MSVC does not understand __builtin_unreachable	Anonymous Maarten	2020-06-17	1	-1/+1
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\| * \| \| \|	MSVC cannot omit operand in conditional	Anonymous Maarten	2020-06-17	1	-1/+1
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\| * \| \| \|	MSVC defines TRANSPARENT too	Anonymous Maarten	2020-06-17	1	-4/+4
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* \| \| \|	Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo	whitequark	2020-06-17	1	-13/+17
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	cxxrtl: restrict the debug info of a blackbox to its ports.
\| * \| \| \|	cxxrtl: restrict the debug info of a blackbox to its ports.	Jean-François Nguyen	2020-06-16	1	-13/+17
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* \| \| \|	Merge pull request #2160 from whitequark/cxxrtl-fix-warning	whitequark	2020-06-17	1	-21/+23
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	cxxrtl: avoid unused variable warning for transparent $memrd ports
\| * \| \| \|	cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC.	whitequark	2020-06-15	1	-21/+23
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* \| \| \| \|	Merge pull request #2156 from XarkLabs/master	N. Engelhardt	2020-06-16	1	-7/+7
\|\ \ \ \ \ \| \|_\|/ / / \|/\| \| \| \|	Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
\| * \| \| \|	Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH	Xark	2020-06-14	1	-7/+7
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* \| \| \| \|	Merge pull request #2159 from MerryMage/cxxrtl-mul	whitequark	2020-06-15	1	-17/+22
\|\ \ \ \ \ \| \|_\|/ / / \|/\| \| \| \|	cxxrtl: Implement chunk-wise multiplication
\| * \| \| \|	cxxrtl: Implement chunk-wise multiplication	MerryMage	2020-06-15	1	-17/+22
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* \| \| \|	Merge pull request #2158 from miek/sshr-sign-extension	whitequark	2020-06-15	1	-2/+4
\|\ \ \ \ \| \|/ / / \|/\| \| \|	cxxrtl: fix sshr sign-extension.
\| * \| \|	cxxrtl: fix sshr sign-extension.	Mike Walters	2020-06-15	1	-2/+4
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* \| \| \|	Merge pull request #2155 from whitequark/fix-wasm-wasi-sdk-11	whitequark	2020-06-13	1	-1/+3
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	kernel: guard include of signal.h more precisely
\| * \| \| \|	kernel: guard include of signal.h more precisely.	whitequark	2020-06-13	1	-1/+3
\|/ / / / \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM does not have signals. (Arguably Yosys was broken even before, it was just broken silently.)
* \| \| \|	Merge pull request #2151 from whitequark/cxxrtl-fix-rzext	whitequark	2020-06-13	1	-2/+2
\|\ \ \ \ \| \|/ / / \|/\| \| \|	cxxrtl: fix rzext()
\| * \| \|	cxxrtl: fix rzext().	whitequark	2020-06-13	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This was a correctness issue, but one of the consequences is that it resulted in jumps in generated machine code where there should have been none. As a side effect of fixing the bug, Minerva SoC became 10% faster.
* \| \| \|	Merge pull request #2145 from whitequark/cxxrtl-splitnets	whitequark	2020-06-13	5	-67/+156
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	cxxrtl: handle multipart signals
\| * \| \| \|	cxxrtl: handle multipart signals.	whitequark	2020-06-11	5	-27/+94
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This avoids losing design visibility when using the `splitnets` pass.
\| * \| \| \|	cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.	whitequark	2020-06-11	3	-40/+62
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* \| \| \|	Merge pull request #2152 from whitequark/cxxrtl-always-inline	whitequark	2020-06-13	1	-4/+108
\|\ \ \ \ \| \|_\|/ / \|/\| \| \|	cxxrtl: always inline internal cells and slice/concat operations
\| * \| \|	cxxrtl: always inline internal cells and slice/concat operations.	whitequark	2020-06-13	1	-4/+108
\|/ / / \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This can result in massive reduction in runtime, up to 50% depending on workload. Currently people are using `-mllvm -inline-threshold=` as a workaround (with clang++), but this solution is more portable.
* \| \|	Merge pull request #2150 from whitequark/cxxrtl-elide-pmux	whitequark	2020-06-12	1	-30/+16
\|\ \ \ \| \| \| \| \| \| \| \|	cxxrtl: elide $pmux cells
\| * \| \|	cxxrtl: elide $pmux cells.	whitequark	2020-06-12	1	-30/+16
\|/ / / \| \| \| \| \| \| \| \| \| \| \| \|	On Minerva, this improves runtime by around 10%, mostly by ensuring that the logic driving FFs is packed into edge conditionals.
* \| \|	Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputs	whitequark	2020-06-12	1	-20/+24
\|\ \ \ \| \| \| \| \| \| \| \|	cxxrtl: unbuffer output wires of toplevel module
\| * \| \|	cxxrtl: annotate port direction as comments.	whitequark	2020-06-12	1	-1/+8
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\| * \| \|	cxxrtl: unbuffer output wires of toplevel module.	whitequark	2020-06-12	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Without unbuffering output wires of, at least, toplevel modules, it is not possible to have most designs that rely on IO via toplevel ports (as opposed to using exclusively blackboxes) converge within one delta cycle. That seriously impairs the performance of CXXRTL. This commit avoids unbuffering outputs of all modules solely so that in future, CXXRTL could gain fully separate compilation, and not for any present technical reason.
\| * \| \|	cxxrtl: simplify unbuffering of input wires.	whitequark	2020-06-12	1	-20/+17
\| \|/ / \| \| \| \| \| \| \| \| \|	This also fixes an edge case with (keep) input ports.
* / /	intel_alm: fix DFFE matching	Dan Ravensloft	2020-06-11	3	-5/+5
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* \|	Merge pull request #2141 from whitequark/cxxrtl-cxx11	whitequark	2020-06-10	3	-8/+10
\|\ \ \| \| \| \| \| \|	cxxrtl: various compiler compatibility fixes
\| * \|	cxxrtl: restore C++11 compatibility.	whitequark	2020-06-10	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \|	This is necessary to be able to build CXXRTL models via yosys-config.
\| * \|	cxxrtl: fix a few gcc warnings.	whitequark	2020-06-10	1	-5/+6
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\| * \|	Fix formatting. NFC.	whitequark	2020-06-10	1	-2/+2
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* \| \|	Merge pull request #2140 from whitequark/cxxrtl-aliases	whitequark	2020-06-10	4	-9/+50
\|\ \ \ \| \|/ / \|/\| \|	cxxrtl: disambiguate values/wires and their aliases in debug info
\| * \|	cxxrtl: disambiguate values/wires and their aliases in debug info.	whitequark	2020-06-10	4	-9/+50
\|/ / \| \| \| \| \| \| \| \| \| \| \| \|	With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation).
* \|	Merge pull request #2134 from whitequark/cxxrtl-opt-debug	whitequark	2020-06-10	1	-52/+105
\|\ \ \| \| \| \| \| \|	cxxrtl: introduce -Og optimization level
\| * \|	cxxrtl: allow unbuffering without localizing.	whitequark	2020-06-09	1	-40/+74
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Although logically two separate steps, these were treated as one for historic reasons. Splitting the two makes it possible to have designs that are only 2× slower than fastest possible (and are without extra delta cycles) that allow probing all public wires.