| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Bugfix in partial mem write handling in verilog back-end | Clifford Wolf | 2016-08-20 | 1 | -42/+26 |
| * | Added missing support for mem read enable ports to verilog back-end | Clifford Wolf | 2016-08-18 | 1 | -6/+14 |
| * | Fixed upto handling in verilog back-end | Clifford Wolf | 2016-08-15 | 1 | -0/+3 |
| * | Added "write_verilog -defparam" | Clifford Wolf | 2016-07-30 | 1 | -2/+21 |
| * | Added "write_verilog -nodec -nostr" | Clifford Wolf | 2016-07-30 | 1 | -4/+27 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Bugfix in write_verilog for RTLIL processes | Clifford Wolf | 2016-03-14 | 1 | -9/+20 |
| * | Bugfixes in writing of memories as Verilog | Clifford Wolf | 2015-09-25 | 1 | -7/+8 |
| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -2/+2 |
| * | Re-created command-reference-manual.tex, copied some doc fixes to online help | Clifford Wolf | 2015-08-14 | 1 | -3/+3 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -4/+4 |
| * | $mem cell in verilog backend : grouped writes by clock | luke whittlesey | 2015-06-08 | 1 | -54/+108 |
| * | Bug fix in $mem verilog backend + changed tests/bram flow of make test. | luke whittlesey | 2015-06-04 | 1 | -14/+16 |
| * | Some fixes for $mem in verilog back-end | Clifford Wolf | 2015-05-20 | 1 | -19/+23 |
| * | Merge pull request #63 from wluker/verilog-backend-mem | Clifford Wolf | 2015-05-11 | 1 | -1/+2 |
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| | * | Fixed bug in $mem cell verilog code generation. | luke whittlesey | 2015-05-11 | 1 | -11/+12 |
| * | | Disabled broken $mem support in verilog backend | Clifford Wolf | 2015-05-10 | 1 | -11/+11 |
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| * | Made changes recommended by Clifford Wolf ... | luke whittlesey | 2015-05-10 | 1 | -22/+11 |
| * | Verilog backend for $mem cells should now be able to handle different | luke whittlesey | 2015-05-08 | 1 | -50/+105 |
| * | Added support for $mem cells in the verilog backend. | luke whittlesey | 2015-05-07 | 1 | -1/+120 |
| * | Minor fixes in handling of "init" attribute | Clifford Wolf | 2015-04-09 | 1 | -7/+7 |
| * | Added "init" attribute support to verilog backend | Clifford Wolf | 2015-04-04 | 1 | -0/+5 |
| * | Added Verilog backend $dffsr support | Clifford Wolf | 2015-03-18 | 1 | -1/+51 |
| * | Fixed "write_verilog -attr2comment" handling of "*/" in strings | Clifford Wolf | 2015-02-13 | 1 | -2/+4 |
| * | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 | 1 | -0/+2 |
| * | Cosmetic changes in verilog output format | Clifford Wolf | 2015-01-02 | 1 | -5/+10 |
| * | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 1 | -25/+25 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
| * | Added $dffe support to write_verilog | Clifford Wolf | 2014-12-20 | 1 | -3/+14 |
| * | Fixed generation of temp names in verilog backend | Clifford Wolf | 2014-11-07 | 1 | -4/+5 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -1/+1 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -4/+3 |
| * | Various bug fixes (related to $macc model testing) | Clifford Wolf | 2014-09-06 | 1 | -1/+2 |
| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+0 |
| * | Using $pos models for $bu0 | Clifford Wolf | 2014-09-03 | 1 | -16/+1 |
| * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -230/+230 |
| * | Fixed AOI/OAI expr handling in verilog backend | Clifford Wolf | 2014-08-16 | 1 | -4/+4 |
| * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 | 1 | -4/+40 |
| * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 1 | -1/+1 |
| * | Refactoring of CellType class | Clifford Wolf | 2014-08-14 | 1 | -10/+28 |
| * | Be more conservative with printing decimal numbers in verilog backend | Clifford Wolf | 2014-08-02 | 1 | -2/+3 |
| * | Improved verilog output for ordinary $mux cells | Clifford Wolf | 2014-08-02 | 1 | -3/+19 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -6/+6 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -40/+40 |
| * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 | 1 | -9/+22 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -3/+2 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -4/+4 |
