iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15	1	-1434/+0
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-0/+1
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*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22	1	-0/+12
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*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21	1	-1/+12
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*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	1	-1/+32
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*	Added support for global tasks and functions	Clifford Wolf	2014-08-21	1	-11/+19
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*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18	1	-12/+14
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*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07	1	-3/+5
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	1	-4/+18
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-2/+1
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04	1	-1/+7
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+5
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*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	1	-0/+7
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*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16	1	-5/+11
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	1	-5/+12
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	1	-3/+14
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	1	-2/+8
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*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+7
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*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06	1	-4/+8
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	1	-1/+27
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*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-0/+1
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*	Added support for functions returning integer	Clifford Wolf	2014-02-12	1	-2/+12
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+22
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-3/+8
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-1/+9
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-12/+1
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-4/+40
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	1	-2/+5
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23	1	-10/+10
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20	1	-0/+11
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-2/+12
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20	1	-6/+19
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19	1	-3/+10
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*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13	1	-2/+2
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-26/+52
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*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-2/+2
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*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-1/+1
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-9/+39
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-2/+12
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*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07	1	-0/+2
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+1
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*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-1/+6
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-10/+16
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*	Added support for "always @(*)"	Clifford Wolf	2013-01-16	1	-0/+3
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+1074