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* Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
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| * verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
* | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
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* Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
* verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
* Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
* sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
* Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
* Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
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| * Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| * Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
* | Merge pull request #2179 from splhack/static-castclairexen2020-07-011-0/+19
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| * | static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+19
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* | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-261-2/+43
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| * | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-251-2/+19
| * | Support missing xor-assign operatorLukasz Dalek2020-06-241-1/+9
| * | Add plus-assignment operatorKamil Rakoczy2020-06-241-1/+9
| * | Add or-assignment operatorKamil Rakoczy2020-06-241-1/+9
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* | Support optional labels at the end of package definitionLukasz Dalek2020-06-241-1/+1
* | Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
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* MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
* Support packed arrays in struct/union.Peter Crozier2020-06-071-5/+5
* Merge branch 'master' into structPeter Crozier2020-06-031-31/+48
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| * verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
| * verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
| * verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| * verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
| * Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
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| | * Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | * verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
| * | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| * | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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* | Allow structs within structs.Peter Crozier2020-05-121-7/+18
* | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-16/+34
* | Implement SV structs.Peter Crozier2020-05-081-101/+180
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* Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-2/+2
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| * Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-2/+2
* | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
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| * | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
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