iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add "verific -L <int>" option	Clifford Wolf	2018-09-04	3	-2/+16
*	Add "make coverage"	Clifford Wolf	2018-08-27	6	-12/+10
*	Merge pull request #610 from udif/udif_specify_round2	Clifford Wolf	2018-08-23	1	-16/+39
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\| *	Fixed all known specify/endspecify issues, without breaking 'make test'.	Udi Finkelstein	2018-08-20	1	-12/+12
\| *	Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...	Udi Finkelstein	2018-08-20	1	-10/+22
\| *	A few minor enhancements to specify block parsing.	Udi Finkelstein	2018-08-15	1	-2/+13
* \|	Added -no_dump_ptr flag for AST dump options in 'read_verilog'	Udi Finkelstein	2018-08-23	3	-9/+20
* \|	Add "verific -work" help message	Clifford Wolf	2018-08-22	1	-0/+7
* \|	Add Verific -work parameter	Clifford Wolf	2018-08-22	1	-8/+18
* \|	Add "verific -set-<severity> <msg_id>.."	Clifford Wolf	2018-08-16	1	-14/+52
* \|	Verific workaround for VIPER ticket 13851	Clifford Wolf	2018-08-16	1	-0/+3
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*	Merge pull request #591 from hzeller/virtual-override	Clifford Wolf	2018-08-15	7	-23/+23
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\| *	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	7	-23/+23
* \|	Merge pull request #590 from hzeller/remaining-file-error	Clifford Wolf	2018-08-15	1	-15/+15
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\| * \|	Fix remaining log_file_error(); emit dependent file references in new line.	Henner Zeller	2018-07-20	1	-15/+15
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* \|	Merge pull request #513 from udif/pr_reg_wire_error	Clifford Wolf	2018-08-15	5	-4/+57
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\| * \|	Modified errors into warnings	Udi Finkelstein	2018-06-05	4	-7/+41
\| * \|	This PR should be the base for discussion, do not merge it yet!	Udi Finkelstein	2018-03-11	5	-4/+23
* \| \|	Merge pull request #562 from udif/pr_fix_illegal_port_decl	Clifford Wolf	2018-08-15	1	-3/+6
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\| * \| \|	Detect illegal port declaration, e.g input/output/inout keyword must be the f...	Udi Finkelstein	2018-06-06	1	-3/+6
* \| \| \|	Fixed use of char array for string in blifparse error handling	Clifford Wolf	2018-08-08	1	-5/+5
* \| \| \|	Report error reason on same line as syntax error.	litghost	2018-08-08	1	-6/+9
* \| \| \|	Use log_warning which does not immediately terminate.	litghost	2018-08-03	1	-3/+3
* \| \| \|	Add BLIF parsing support for .conn and .cname	litghost	2018-08-02	1	-3/+30
* \| \| \|	Verific: Produce errors for instantiating unknown module	Clifford Wolf	2018-07-22	1	-0/+3
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* \| \|	Convert more log_error() to log_file_error() where possible.	Henner Zeller	2018-07-20	4	-137/+131
* \| \|	Use log_file_warning(), log_file_error() functions.	Henner Zeller	2018-07-20	3	-82/+79
* \| \|	Provide source-location logging.	Henner Zeller	2018-07-19	1	-3/+2
* \| \|	Fix handling of eventually properties in verific importer	Clifford Wolf	2018-07-17	1	-2/+4
* \| \|	Fix verific -vlog-incdir and -vlog-libdir handling	Clifford Wolf	2018-07-16	1	-2/+13
* \| \|	Fix "read -incdir"	Clifford Wolf	2018-07-16	1	-1/+1
* \| \|	Add "read -incdir"	Clifford Wolf	2018-07-16	1	-0/+19
* \| \|	Fix verific eventually handling	Clifford Wolf	2018-06-29	1	-6/+5
* \| \|	Add verific support for eventually properties	Clifford Wolf	2018-06-29	1	-5/+105
* \| \|	Add "verific -formal" and "read -formal"	Clifford Wolf	2018-06-29	1	-7/+15
* \| \|	Add "read -sv -D" support	Clifford Wolf	2018-06-28	1	-2/+25
* \| \|	Add "read -undef"	Clifford Wolf	2018-06-28	1	-0/+32
* \| \|	Fix handling of signed memories	Clifford Wolf	2018-06-28	1	-0/+3
* \| \|	Add YOSYS_NOVERIFIC env variable for temporarily disabling verific	Clifford Wolf	2018-06-22	1	-22/+40
* \| \|	Add simplified "read" command, enable extnets in implicit Verific import	Clifford Wolf	2018-06-21	1	-0/+84
* \| \|	Add automatic verific import in hierarchy command	Clifford Wolf	2018-06-20	2	-0/+56
* \| \|	Bugfix in liberty parser (as suggested by aiju in #569)	Clifford Wolf	2018-06-15	1	-1/+1
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* \|	Add (* gclk *) attribute support	Clifford Wolf	2018-06-01	3	-0/+20
* \|	Add comment to VIPER #13453 work-around	Clifford Wolf	2018-05-28	1	-0/+1
* \|	Fix Verific handling of single-bit anyseq/anyconst wires	Clifford Wolf	2018-05-25	1	-2/+4
* \|	Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE	Clifford Wolf	2018-05-24	1	-1/+1
* \|	Fix verific handling of anyconst/anyseq attributes	Clifford Wolf	2018-05-24	2	-16/+28
* \|	Support SystemVerilog `` extension for macros	Jim Paris	2018-05-17	1	-1/+5
* \|	Skip spaces around macro arguments	Jim Paris	2018-05-17	1	-0/+1
* \|	Fix handling of anyconst/anyseq attrs in VHDL code via Verific	Clifford Wolf	2018-05-15	1	-6/+6