iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Do not eagerly fix port widths on parameterized cells	Clifford Wolf	2017-02-12	1	-0/+3
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*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-1/+1
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*	passes/hierarchy: delete some dead code	Austin Seipp	2017-01-15	1	-4/+0
\| \| \| \|	Signed-off-by: Austin Seipp <aseipp@pobox.com>
*	Added cell port resizing to hierarchy pass	Clifford Wolf	2017-01-01	1	-0/+56
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*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-1/+1
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*	Bugfix in "hierarchy -check"	Clifford Wolf	2016-11-02	1	-1/+1
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*	Added avail params to ilang format, check module params in 'hierarchy -check'	Clifford Wolf	2016-10-22	1	-0/+4
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*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+1
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*	Fixed use-after-free dict<> usage pattern in hierarchy.cc	Clifford Wolf	2016-08-16	1	-1/+3
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*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-1/+1
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*	Made the expansion order of hierarchy deterministic	Marcus Comstedt	2016-05-22	1	-3/+3
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-4/+4
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*	Cleanup abstract modules at end of "hierarchy -top"	Clifford Wolf	2016-03-21	1	-2/+0
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-5/+5
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
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*	Keep modules with $assume (like $assert)	Clifford Wolf	2015-07-25	1	-1/+1
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
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*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04	1	-2/+2
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*	documentation improvements	Clifford Wolf	2015-03-29	1	-1/+1
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*	Added hierarchy -auto-top	Clifford Wolf	2015-03-18	1	-1/+33
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*	Fixed bug in "hierarchy" for parametric designs	Clifford Wolf	2015-03-04	1	-20/+19
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*	Cosmetic fixes in "hierarchy" for blackbox modules	Clifford Wolf	2015-02-15	1	-2/+4
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*	Fixed pattern matching in "hierarchy -generate"	Clifford Wolf	2015-01-04	1	-2/+2
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-2/+2
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*	Fixed off-by-one bug in "hierarchy -check" for positional module args	Clifford Wolf	2014-12-24	1	-2/+2
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*	Checking existence of ports in "hierarchy -check"	Clifford Wolf	2014-12-19	1	-0/+13
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*	Fixed bug in "hierarchy -top" with array of instances	Clifford Wolf	2014-11-27	1	-3/+10
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*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17	1	-2/+2
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*	Header changes so it will compile on VS	William Speirs	2014-10-17	1	-1/+5
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*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	1	-1/+1
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*	Moved patmatch() to yosys.cc	Clifford Wolf	2014-10-10	1	-1/+0
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*	Replaced fnmatch() with patmatch()	Clifford Wolf	2014-10-10	1	-5/+4
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*	set "keep" on modules with $assert cells in "hierarchy"	Clifford Wolf	2014-09-30	1	-0/+30
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-11/+13
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*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-4/+4
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*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+2
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-15/+15
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29	1	-1/+3
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+2
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-30/+30
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-5/+5
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-4/+4
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-4/+1
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+2
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-5/+5
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-5/+5
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
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