| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Add warnings for driver-driver conflicts between FFs (and other cells) and ↵ | Clifford Wolf | 2017-12-12 | 1 | -2/+3 |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -7/+19 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -2/+2 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -5/+9 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -44/+44 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -3/+3 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -2/+1 |
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| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -6/+6 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -45/+45 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -45/+45 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -52/+13 |
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| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -1/+1 |
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| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -4/+0 |
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| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -41/+41 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -41/+41 |
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| * | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 | 1 | -10/+10 |
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| * | Do not create $dffsr cells with no-op resets in proc_dff | Clifford Wolf | 2014-06-19 | 1 | -0/+5 |
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| * | Added support for complex set-reset flip-flops in proc_dff | Clifford Wolf | 2013-10-24 | 1 | -4/+115 |
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| * | Improved handling of dff with async resets | Clifford Wolf | 2013-10-21 | 1 | -5/+60 |
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| * | Added dffsr support to proc_dff pass | Clifford Wolf | 2013-10-18 | 1 | -7/+72 |
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| * | fixed typos | Johann Glaser | 2013-03-18 | 1 | -2/+2 |
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| * | Added help messages to proc_* passes | Clifford Wolf | 2013-03-01 | 1 | -6/+18 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+178 |
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index : iCE40/yosys | |
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