iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	shregmap: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-39/+10
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*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
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*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-16/+16
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*	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-30	1	-1/+1
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\| *	Fix typo that's gone unnoticed for 5 months!?!	Eddie Hung	2019-08-29	1	-1/+1
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* \|	Actually, there might not be any harm in updating sigmap...	Eddie Hung	2019-08-22	1	-3/+1
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* \|	Add comment as per @cliffordwolf	Eddie Hung	2019-08-22	1	-0/+11
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* \|	Revert "Try way that doesn't involve creating a new wire"	Eddie Hung	2019-08-22	1	-15/+10
\| \| \| \| \| \| \| \|	This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b.
* \|	Try way that doesn't involve creating a new wire	Eddie Hung	2019-08-22	1	-10/+15
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* \|	If d_bit already in sigbit_chain_next, create extra wire	Eddie Hung	2019-08-22	1	-3/+6
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* \|	Remove `shregmap -tech xilinx` additions	Eddie Hung	2019-08-22	1	-189/+8
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*	Use ID::keep more liberally too	Eddie Hung	2019-08-15	1	-2/+2
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*	Use more ID::{A,B,Y,blackbox,whitebox}	Eddie Hung	2019-08-15	1	-11/+11
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*	ID(\\.) -> ID(.)	Eddie Hung	2019-08-15	1	-54/+54
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*	Transform all "\\*" identifiers into ID()	Eddie Hung	2019-08-15	1	-54/+54
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*	Transform "$." to ID("$.") in passes/techmap	Eddie Hung	2019-08-15	1	-21/+21
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*	More use of IdString::in()	Eddie Hung	2019-08-15	1	-1/+1
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*	Merge pull request #1085 from YosysHQ/eddie/shregmap_improve	Eddie Hung	2019-06-21	1	-3/+15
\|\ \| \| \| \|	Improve shregmap to handle case where first flop is common to two chains
\| *	Actually, there might not be any harm in updating sigmap...	Eddie Hung	2019-06-20	1	-3/+1
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\| *	Add comment as per @cliffordwolf	Eddie Hung	2019-06-20	1	-0/+11
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\| *	Revert "Try way that doesn't involve creating a new wire"	Eddie Hung	2019-06-11	1	-15/+10
\| \| \| \| \| \| \| \|	This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b.
\| *	Try way that doesn't involve creating a new wire	Eddie Hung	2019-06-11	1	-10/+15
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\| *	If d_bit already in sigbit_chain_next, create extra wire	Eddie Hung	2019-06-10	1	-3/+6
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* \|	Improve shregmap help message, fixes #1113	Clifford Wolf	2019-06-20	1	-0/+2
\|/ \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Missing doc for -tech xilinx in shregmap	Eddie Hung	2019-06-05	1	-0/+3
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*	Copy with 1'bx padding in $shiftx	Eddie Hung	2019-04-28	1	-1/+11
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*	Use new pmux2shiftx from #944, remove my old attempt	Eddie Hung	2019-04-21	1	-52/+0
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*	$_XILINX_SHREG_ to preserve src attribute	Eddie Hung	2019-04-08	1	-0/+1
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*	Cope with undoing #895	Eddie Hung	2019-04-08	1	-14/+26
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*	Revert "Remove handling for $pmux, since #895"	Eddie Hung	2019-04-08	1	-0/+40
\| \| \| \|	This reverts commit aa693d5723ef1438d42cd35a26673703b1eff79f.
*	Call shregmap twice -- once for variable, another for fixed	Eddie Hung	2019-04-05	1	-29/+17
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*	Remove handling for $pmux, since #895	Eddie Hung	2019-04-03	1	-40/+0
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*	Cope with SHREG not having E port; Revert $pmux fine tune	Eddie Hung	2019-03-23	1	-4/+3
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*	Add support for SHREGMAP+$mux, also fine tune $pmux	Eddie Hung	2019-03-22	1	-1/+24
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*	Leftover printf	Eddie Hung	2019-03-22	1	-1/+0
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*	Fixes for multibit	Eddie Hung	2019-03-22	1	-18/+38
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*	Working for 1 bit	Eddie Hung	2019-03-22	1	-11/+49
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*	Opt	Eddie Hung	2019-03-21	1	-1/+1
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*	Fix spacing	Eddie Hung	2019-03-20	1	-239/+239
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*	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	1	-5/+14
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*	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	1	-6/+0
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*	shregmap -tech xilinx to delete $shiftx for var length SRL	Eddie Hung	2019-03-19	1	-10/+3
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*	Make output port a non chain user	Eddie Hung	2019-03-19	1	-2/+4
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*	Fix shregmap to correctly recognise non chain users; cleanup	Eddie Hung	2019-03-18	1	-17/+15
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*	shiftx NULL pointer check	Eddie Hung	2019-03-18	1	-8/+10
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*	Cleanup	Eddie Hung	2019-03-16	1	-35/+25
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*	Only accept <128 for variable length, only if $shiftx exclusive	Eddie Hung	2019-03-16	1	-8/+17
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*	Working	Eddie Hung	2019-03-15	1	-227/+356
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*	Revert "Add shregmap -init_msb_first and use in synth_xilinx"	Eddie Hung	2019-03-14	1	-14/+2
\| \| \| \|	This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.