| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 1 | -0/+1 |
| | | | | | Fixes #2058. | ||||
| * | ice40: split out cells_map.v into ff_map.v | Eddie Hung | 2020-05-14 | 1 | -31/+0 |
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| * | xilinx/ice40/ecp5: undo permuting LUT masks in lut_map | Eddie Hung | 2020-01-27 | 1 | -7/+6 |
| | | | | | Now done in read_aiger | ||||
| * | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -19/+0 |
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| * | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 |
| | | | | | name and attr | ||||
| * | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| * | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 1 | -14/+9 |
| | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | ||||
| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 1 | -9/+14 |
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| * | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 1 | -8/+5 |
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| * | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 1 | -12/+10 |
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| * | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
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| * | _ABC macro will map and unmap to this new box | Eddie Hung | 2019-07-12 | 1 | -0/+24 |
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| * | Ooopsie | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
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| * | Map to SB_LUT4 from fastest input first | Eddie Hung | 2019-04-17 | 1 | -7/+11 |
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| * | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" | Eddie Hung | 2019-04-17 | 1 | -24/+0 |
| | | | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253. | ||||
| * | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | Eddie Hung | 2019-04-17 | 1 | -0/+24 |
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| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -1/+1 |
| | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | ||||
| * | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 1 | -0/+2 |
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| * | improved ice40 dff cell mapping | Clifford Wolf | 2015-04-16 | 1 | -3/+28 |
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| * | Added very first version of "synth_ice40" | Clifford Wolf | 2015-03-05 | 1 | -0/+32 |
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index : iCE40/yosys | |
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