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* LX -> LPEddie Hung2019-08-281-1/+1
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* Specify ice40 family to cells_sim.v using defineEddie Hung2019-08-281-1/+8
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* Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-121-6/+7
| | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-7/+6
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* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-101-1/+1
|\ | | | | Cleanup a few barnacles across codebase
| * stoi -> atoiEddie Hung2019-08-071-1/+1
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* | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-071-1/+3
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* | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-071-5/+4
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* Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-181-2/+2
|\ | | | | synth_{ice40,ecp5}: more sensible pass label naming
| * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-161-2/+2
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* | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-161-2/+3
|\ \ | |/ |/| abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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* | synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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* | synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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* Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-1/+4
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* Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
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* Extraneous newlineEddie Hung2019-06-271-1/+0
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* abc9: Add wire delays to synth_ice40David Shah2019-06-261-2/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Resolve comments from @daveshah1Eddie Hung2019-06-141-1/+1
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* Make doc consistentEddie Hung2019-06-141-1/+1
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* Consistent with xilinxEddie Hung2019-06-031-2/+2
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* Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7muxEddie Hung2019-05-021-0/+2
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| * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-301-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-021-4/+6
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| * | Cleanup ice40Eddie Hung2019-04-261-4/+6
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* | Convert to use #945Eddie Hung2019-04-211-1/+1
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* | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL setEddie Hung2019-04-191-1/+1
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* | Fix SB_DFF comb modelEddie Hung2019-04-181-2/+2
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* | Use new -wb flag for ABC flowEddie Hung2019-04-181-7/+3
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* | Reduce to three devices: hx, lp, uEddie Hung2019-04-171-4/+4
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* | Update error messageEddie Hung2019-04-171-1/+1
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* | Add "-device" argument to synth_ice40Eddie Hung2019-04-171-2/+13
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* | synth_ice40 to use renamed filesEddie Hung2019-04-171-2/+2
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* | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"Eddie Hung2019-04-171-1/+1
| | | | | | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
* | Try using an ICE40_CARRY_LUT primitive to avoid ABC issuesEddie Hung2019-04-171-1/+1
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* | Add ice40 box filesEddie Hung2019-04-161-1/+8
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* | Merge branch 'master' into xaigEddie Hung2019-04-081-0/+1
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| * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-261-1/+1
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| * Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-221-1/+1
| |\ | | | | | | Improve ABC netname preservation
| | * ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-211-3/+28
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| * | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / synth_ice40 to have new -abc9 argEddie Hung2019-02-141-4/+12
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* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-1/+1
|\ | | | | synth: add k-LUT mode
| * synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
|/ | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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