| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | Run "peepopt" in generic "synth" pass and "synth_ice40" | Clifford Wolf | 2019-04-30 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-02 | 1 | -4/+6 | |
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| | * | | Cleanup ice40 | Eddie Hung | 2019-04-26 | 1 | -4/+6 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -10/+19 | |
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| | * | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵ | Luke Wren | 2019-04-21 | 1 | -10/+19 | |
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| * | | Convert to use #945 | Eddie Hung | 2019-04-21 | 2 | -9/+3 | |
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| * | | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set | Eddie Hung | 2019-04-19 | 2 | -4/+7 | |
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| * | | Make SB_DFF whitebox | Eddie Hung | 2019-04-19 | 3 | -3/+3 | |
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| * | | Fix SB_DFF comb model | Eddie Hung | 2019-04-18 | 2 | -3/+3 | |
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| * | | Missing close bracket | Eddie Hung | 2019-04-18 | 1 | -1/+1 | |
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| * | | Annotate SB_DFF* with abc_flop and abc_box_id | Eddie Hung | 2019-04-18 | 1 | -22/+49 | |
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| * | | Add SB_DFF* to boxes | Eddie Hung | 2019-04-18 | 3 | -6/+306 | |
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| * | | Use new -wb flag for ABC flow | Eddie Hung | 2019-04-18 | 3 | -19/+5 | |
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| * | | Also update Makefile.inc | Eddie Hung | 2019-04-18 | 1 | -7/+6 | |
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| * | | Make SB_LUT4 a blackbox | Eddie Hung | 2019-04-18 | 3 | -3/+3 | |
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| * | | Fix rename | Eddie Hung | 2019-04-18 | 1 | -0/+0 | |
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| * | | Rename to abc_*.{box,lut} | Eddie Hung | 2019-04-18 | 6 | -0/+0 | |
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| * | | Update Makefile.inc too | Eddie Hung | 2019-04-17 | 1 | -4/+6 | |
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| * | | Reduce to three devices: hx, lp, u | Eddie Hung | 2019-04-17 | 7 | -4/+23 | |
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| * | | Add up5k timings | Eddie Hung | 2019-04-17 | 2 | -0/+19 | |
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| * | | Update error message | Eddie Hung | 2019-04-17 | 1 | -1/+1 | |
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| * | | Add "-device" argument to synth_ice40 | Eddie Hung | 2019-04-17 | 4 | -7/+20 | |
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| * | | Missing abc_flop_q attribute on SPRAM | Eddie Hung | 2019-04-17 | 1 | -1/+1 | |
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| * | | Map to SB_LUT4 from fastest input first | Eddie Hung | 2019-04-17 | 1 | -7/+11 | |
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| * | | Mark seq output ports with "abc_flop_q" attr | Eddie Hung | 2019-04-17 | 1 | -24/+24 | |
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| * | | Also update Makefile.inc | Eddie Hung | 2019-04-17 | 1 | -3/+3 | |
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| * | | synth_ice40 to use renamed files | Eddie Hung | 2019-04-17 | 1 | -2/+2 | |
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| * | | Rename to abc.* | Eddie Hung | 2019-04-17 | 3 | -0/+0 | |
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| * | | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" | Eddie Hung | 2019-04-17 | 7 | -102/+35 | |
| | | | | | | | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253. | |||||
| * | | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | Eddie Hung | 2019-04-17 | 7 | -35/+102 | |
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| * | | Fix spacing | Eddie Hung | 2019-04-17 | 1 | -5/+5 | |
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| * | | Add SB_LUT4 to box library | Eddie Hung | 2019-04-16 | 3 | -0/+16 | |
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| * | | Add ice40 box files | Eddie Hung | 2019-04-16 | 6 | -1/+27 | |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 5 | -42/+198 | |
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| | * | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix typo in ice40_braminit help msg | Clifford Wolf | 2019-03-09 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge pull request #859 from smunaut/ice40_braminit | Clifford Wolf | 2019-03-09 | 4 | -37/+212 | |
| | |\ | | | | | | | iCE40 BRAM primitives init from file | |||||
| | | * | ice40: Run ice40_braminit pass by default | Sylvain Munaut | 2019-03-08 | 1 | -0/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| | | * | ice40: Add ice40_braminit pass to allow initialization of BRAM from file | Sylvain Munaut | 2019-03-08 | 3 | -37/+211 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| | * | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 | |
| | |/ | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net> | |||||
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 1 | -1/+1 | |
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| | * | Merge pull request #740 from daveshah1/improve_dress | Clifford Wolf | 2019-02-22 | 1 | -1/+1 | |
| | |\ | | | | | | | Improve ABC netname preservation | |||||
| | | * | ice40: Use abc -dress in synth_ice40 | David Shah | 2019-02-06 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-21 | 6 | -58/+667 | |
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| | * | | Bugfix in ice40_dsp | Clifford Wolf | 2019-02-21 | 2 | -20/+33 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add ice40 test_dsp_map test case generator | Clifford Wolf | 2019-02-20 | 2 | -0/+99 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add "synth_ice40 -dsp" | Clifford Wolf | 2019-02-20 | 1 | -3/+27 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve iCE40 SB_MAC16 model | Clifford Wolf | 2019-02-20 | 5 | -121/+179 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add first draft of functional SB_MAC16 model | Clifford Wolf | 2019-02-19 | 4 | -53/+467 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * / | synth_ice40 to have new -abc9 arg | Eddie Hung | 2019-02-14 | 1 | -4/+12 | |
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index : iCE40/yosys | |
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