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* Convert to use #945Eddie Hung2019-04-212-9/+3
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* ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL setEddie Hung2019-04-192-4/+7
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* Make SB_DFF whiteboxEddie Hung2019-04-193-3/+3
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* Fix SB_DFF comb modelEddie Hung2019-04-182-3/+3
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* Missing close bracketEddie Hung2019-04-181-1/+1
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* Annotate SB_DFF* with abc_flop and abc_box_idEddie Hung2019-04-181-22/+49
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* Add SB_DFF* to boxesEddie Hung2019-04-183-6/+306
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* Use new -wb flag for ABC flowEddie Hung2019-04-183-19/+5
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* Also update Makefile.incEddie Hung2019-04-181-7/+6
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* Make SB_LUT4 a blackboxEddie Hung2019-04-183-3/+3
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* Fix renameEddie Hung2019-04-181-0/+0
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* Rename to abc_*.{box,lut}Eddie Hung2019-04-186-0/+0
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* Update Makefile.inc tooEddie Hung2019-04-171-4/+6
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* Reduce to three devices: hx, lp, uEddie Hung2019-04-177-4/+23
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* Add up5k timingsEddie Hung2019-04-172-0/+19
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* Update error messageEddie Hung2019-04-171-1/+1
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* Add "-device" argument to synth_ice40Eddie Hung2019-04-174-7/+20
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* Missing abc_flop_q attribute on SPRAMEddie Hung2019-04-171-1/+1
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* Map to SB_LUT4 from fastest input firstEddie Hung2019-04-171-7/+11
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* Mark seq output ports with "abc_flop_q" attrEddie Hung2019-04-171-24/+24
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* Also update Makefile.incEddie Hung2019-04-171-3/+3
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* synth_ice40 to use renamed filesEddie Hung2019-04-171-2/+2
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* Rename to abc.*Eddie Hung2019-04-173-0/+0
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* Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"Eddie Hung2019-04-177-102/+35
| | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
* Try using an ICE40_CARRY_LUT primitive to avoid ABC issuesEddie Hung2019-04-177-35/+102
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* Fix spacingEddie Hung2019-04-171-5/+5
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* Add SB_LUT4 to box libraryEddie Hung2019-04-163-0/+16
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* Add ice40 box filesEddie Hung2019-04-166-1/+27
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* Merge branch 'master' into xaigEddie Hung2019-04-085-42/+198
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| * Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
| |\ | | | | | | iCE40 BRAM primitives init from file
| | * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| | * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| |/ | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-261-1/+1
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| * Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-221-1/+1
| |\ | | | | | | Improve ABC netname preservation
| | * ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-216-58/+667
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| * | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / synth_ice40 to have new -abc9 argEddie Hung2019-02-141-4/+12
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* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-1/+1
|\ | | | | synth: add k-LUT mode
| * synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
|/ | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
|\ | | | | equiv_opt: new command, for verifying optimization passes
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