iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	2	-2/+2
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	Fix duplicated parameter name typo	Miodrag Milanovic	2020-11-18	1	-1/+1
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*	intel: Use dfflegalize.	Marcelina Kościelnicka	2020-07-13	1	-0/+11
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*	intel: Map M9K BRAM only on families that have it	Dan Ravensloft	2019-07-23	2	-0/+0
\| \| \| \| \| \| \| \|	This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
*	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	1	-8/+8
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*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	4	-39/+39
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*	Tested and working altsyncarm without init files	dh73	2017-10-01	2	-57/+59
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*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵	dh73	2017-10-01	4	-0/+560
	M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now