iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: M10K write-enable is negative-true	Lofty	2022-03-09	1	-2/+2
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*	intel_alm: disable 256x40 M10K mode	Lofty	2021-12-22	1	-9/+3
\| \| \| \| \|	This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	1	-2/+2
\| \| \| \|	This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	1	-2/+2
\| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	1	-2/+2
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+33
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).