iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: preliminary Arria V support	Lofty	2021-11-25	1	-0/+15
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*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	1	-1/+3
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	1	-27/+28
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*	Improve MISTRAL_FF specify rules	Dan Ravensloft	2020-07-04	1	-5/+4
\| \| \| \|	Co-authored-by: Eddie Hung <eddie@fpgeh.com>
*	intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF	Eddie Hung	2020-07-04	1	-1/+1
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*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	1	-10/+32
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*	intel_alm: Documentation improvements	Dan Ravensloft	2020-04-21	1	-0/+44
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+48
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).