| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Test fixes for latest iverilog | Miodrag Milanovic | 2022-09-21 | 1 | -1/+1 |
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| * | sf2: suport $alu gate and ARI1 implementation | Tristan Gingold | 2022-08-31 | 1 | -1/+16 |
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| * | sf2/cells_sim.v: add XTLOSC, SYSRESET cells | Tristan Gingold | 2022-08-31 | 1 | -1/+110 |
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| * | sf2/cells_sim.v: add IOSTD parameter to I/O cells | Tristan Gingold | 2022-08-31 | 1 | -0/+11 |
| | | | | | | This parameter is set by LiberoSoc IPs, so it is needed to avoid errors when using those IPs. | ||||
| * | sf2: fix name of AND modules | Stefan Riesenberger | 2021-04-09 | 1 | -3/+3 |
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| * | sf2: replace sf2_iobs with {clkbuf,iopad}map | Dan Ravensloft | 2020-07-09 | 1 | -12/+129 |
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| * | Add link to SF2 / igloo2 macro library guide | Clifford Wolf | 2019-03-07 | 1 | -21/+24 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Improvements in sf2 cells_sim.v | Clifford Wolf | 2019-03-06 | 1 | -28/+249 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Refactor SF2 iobuf insertion, Add clkint insertion | Clifford Wolf | 2019-03-06 | 1 | -0/+7 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add SF2 IO buffer insertion | Clifford Wolf | 2019-01-17 | 1 | -0/+21 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix sf2 LUT interface | Clifford Wolf | 2018-10-31 | 1 | -8/+8 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Basic SmartFusion2 and IGLOO2 synthesis support | Clifford Wolf | 2018-10-31 | 1 | -0/+75 |
| Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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index : iCE40/yosys | |
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