iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-447/+0
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*	Add techmap_autopurge to outputs in abc_map.v too	Eddie Hung	2019-09-23	1	-11/+11
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*	Tidy up, fix undriven	Eddie Hung	2019-09-19	1	-32/+34
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*	$__ABC_REG to have WIDTH parameter	Eddie Hung	2019-09-19	1	-16/+16
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*	Fix DSP48E1 timing by breaking P path if MREG or PREG	Eddie Hung	2019-09-19	1	-30/+27
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*	Revert "Different approach to timing"	Eddie Hung	2019-09-19	1	-80/+61
\| \| \| \|	This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
*	Different approach to timing	Eddie Hung	2019-09-19	1	-61/+80
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*	Suppress $anyseq warnings	Eddie Hung	2019-09-19	1	-15/+32
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*	Use (* techmap_autopurge *) to suppress techmap warnings	Eddie Hung	2019-09-19	1	-55/+55
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*	Fix copy-paste	Eddie Hung	2019-09-18	1	-2/+2
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*	Add `undef DSP48E1_INST	Eddie Hung	2019-09-13	1	-4/+5
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*	Add no MULT no DPORT config	Eddie Hung	2019-09-13	1	-127/+91
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*	Add support for MULT and DPORT	Eddie Hung	2019-09-13	1	-4/+130
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*	Rename to techmap_guard	Eddie Hung	2019-09-12	1	-2/+3
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*	Initial DSP48E1 box support	Eddie Hung	2019-09-12	1	-0/+216
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*	Resolve TODO with pin assignments for SRL*	Eddie Hung	2019-09-04	1	-4/+2
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*	xilinx to use abc_map.v with -max_iter 1	Eddie Hung	2019-08-20	1	-13/+13
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*	Remove sequential extension	Eddie Hung	2019-08-20	1	-97/+0
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*	LUTMUX -> LUTMUX6	Eddie Hung	2019-08-20	1	-2/+2
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*	Remove delays from abc_map.v	Eddie Hung	2019-08-20	1	-5/+2
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*	Typo	Eddie Hung	2019-08-20	1	-1/+1
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*	Wrap SRL{16,32} too	Eddie Hung	2019-08-20	1	-0/+36
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*	Wrap LUTRAMs in order to capture comb/seq behaviour	Eddie Hung	2019-08-20	1	-0/+69
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*	Use abc_{map,unmap,model}.v	Eddie Hung	2019-08-20	1	-0/+120