| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -24/+79 |
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| | * | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -24/+91 |
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| | | * | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 |
| | | * | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| | | * | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| | | | * | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | | * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 |
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| | | | * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -7/+14 |
| | | * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -14/+20 |
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| | | * | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -33/+42 |
| | | * | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+16 |
| * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -8/+20 |
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| | * | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
| | * | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 |
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| * | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 |
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| * | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 |
| * | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 1 | -1/+1 |
| * | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 1 | -5/+8 |
| * | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 1 | -6/+13 |
| * | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 1 | -2/+3 |
| * | | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -2/+2 |
| * | | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -40/+49 |
| * | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 |
| * | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 |
| * | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 |
| * | | Signedness | Eddie Hung | 2019-07-16 | 1 | -7/+7 |
| * | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
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| | * | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 |
| * | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 |
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| * / | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim | Eddie Hung | 2019-07-15 | 1 | -0/+131 |
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| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv... | Marcin Kościelnicki | 2019-07-11 | 1 | -2/+2 |
| * | Revert "Fix broken MUXFx box, use MUXF7x2 box instead" | Eddie Hung | 2019-07-01 | 1 | -3/+3 |
| * | Fix broken MUXFx box, use MUXF7x2 box instead | Eddie Hung | 2019-07-01 | 1 | -3/+3 |
| * | Fix CARRY4 abc_box_id | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-28 | 1 | -2/+2 |
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| | * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -2/+2 |
| | * | Merge origin/master | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
| * | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-26 | 1 | -3/+3 |
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| | * | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 |
| | * | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 1 | -2/+3 |
| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-25 | 1 | -0/+17 |
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| * | \ | Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| | * | | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 1 | -1/+1 |
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| * | | | Cleanup abc_box_id | Eddie Hung | 2019-06-26 | 1 | -5/+5 |
| * | | | Add RAM32X1D box info | Eddie Hung | 2019-06-24 | 1 | -2/+3 |
| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-24 | 1 | -0/+2 |
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| | * | | Add Xilinx dist RAM as comb boxes | Eddie Hung | 2019-06-24 | 1 | -0/+2 |
| * | | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux | Eddie Hung | 2019-06-24 | 1 | -0/+17 |
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| | * | | Add RAM32X1D support | Eddie Hung | 2019-06-24 | 1 | -0/+17 |
| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-22 | 1 | -2/+0 |
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