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path: root/techlibs/xilinx/synth_xilinx.cc
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* synth_xilinx to now wreduce except $mux, remove extra peepoptEddie Hung2019-06-211-8/+1
* Restore wreduce to synth_xilinx, after muxcoverEddie Hung2019-06-211-0/+1
* synth_xilinx to use _ABC macro, and perform muxpack againEddie Hung2019-06-211-5/+5
* Fix alignmentEddie Hung2019-06-211-1/+1
* Add FIXME about need for -mux4Eddie Hung2019-06-211-0/+2
* Expand synth -coarse without wreduce, move muxcoverEddie Hung2019-06-211-12/+24
* Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
* Try -W 300Eddie Hung2019-06-161-1/+2
* Revert "Remove wide mux inference"Eddie Hung2019-06-141-3/+21
* Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
* Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-141-1/+1
* Make doc consistentEddie Hung2019-06-141-1/+1
* Reduce diff with masterEddie Hung2019-06-121-1/+1
* Fix spacingEddie Hung2019-06-121-6/+6
* Remove wide mux inferenceEddie Hung2019-06-121-21/+3
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-121-168/+154
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| * Remove extra newlineEddie Hung2019-06-031-1/+0
| * Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
| * Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
| * Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| * Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
| * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-011-165/+97
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| | * Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
| * | WIPEddie Hung2019-04-281-36/+22
| * | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
| * | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-13/+45
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| * Update help messageEddie Hung2019-04-221-1/+1
| * Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
| * Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-221-0/+2
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| * | Tidy up, fix for -nosrlEddie Hung2019-04-211-8/+7
| * | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * | | Add commentsEddie Hung2019-04-211-0/+7
| * | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
| * | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-051-8/+11
| * | | Move dffinit til after abcEddie Hung2019-04-051-2/+2
| * | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-051-7/+8
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| * | | | techmap inside map_cells stageEddie Hung2019-04-051-1/+1
| * | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * \ \ \ \ Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| * | | | | | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
| * | | | | | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
| * | | | | | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
| * | | | | | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
| * | | | | | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
| * | | | | | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * | | | | | | Cleanup synth_xilinxEddie Hung2019-03-151-2/+1
| * | | | | | | WorkingEddie Hung2019-03-151-7/+9
| * | | | | | | MisspellEddie Hung2019-03-141-1/+1
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