| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Remove "opt_expr -fine" call | Eddie Hung | 2019-09-10 | 1 | -1/+0 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -9/+12 |
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| | * | Merge branch 'eddie/xilinx_srl' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -15/+22 |
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| | * \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -1/+53 |
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| | * | | | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| | * | | | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| | * | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| | * | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -5/+1 |
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| | * | | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 |
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| | * | | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -14/+17 |
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| | * | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| | * | | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -6/+6 |
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| | * | | | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 1 | -6/+21 |
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| | * | | | | | Move ABC FF stuff to abc_ff.v; add support for other FD* types | Eddie Hung | 2019-07-10 | 1 | -1/+1 |
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| | * | | | | | synth_xilinx's map_cells stage to techmap ff_map.v | Eddie Hung | 2019-07-10 | 1 | -0/+2 |
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| | * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-10 | 1 | -30/+103 |
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| | * \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-01 | 1 | -27/+46 |
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| | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/xaig' into xaig_dff | Eddie Hung | 2019-06-17 | 1 | -1/+2 |
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| | * | | | | | | | | Fix initialisation of flops | Eddie Hung | 2019-06-15 | 1 | -11/+11 |
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| | * | | | | | | | | Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues | Eddie Hung | 2019-06-15 | 1 | -1/+1 |
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| | * | | | | | | | | Wrap FDRE with $__ABC_FDRE containing comb | Eddie Hung | 2019-06-15 | 1 | -7/+15 |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -14/+23 |
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 1 | -1/+45 |
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| | * | | | | | | | | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
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| | * | | | | | | | | | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 |
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| | * | | | | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 |
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| | * | | | | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 |
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| | * | | | | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -1/+52 |
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| | * \ \ \ \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -13/+68 |
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| | | * | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
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| | | | * | | | | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 |
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| | | * | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -14/+17 |
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| | | * | | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 |
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| | | * | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 |
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| | | * | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+36 |
| | | | |_|_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | ||||
| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -14/+17 |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| | * | | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 1 | -14/+17 |
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| * | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 |
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| | * | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | | | | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
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| * | | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
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| * | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 |
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| * | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 |
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| * | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
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| * | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
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index : iCE40/yosys | |
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